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AD8224ACPZ-R7 Datasheet(PDF) 19 Page - Analog Devices |
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AD8224ACPZ-R7 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 27 page ![]() Preliminary Technical Data AD8224 15 60 SETTL SETTLED T ED TO 0.001% O 0.01% GAIN = +1000 +100 GAIN = +10 GAIN = +1 GAIN = 40 10 20 0 5 –20 0 –40 0 5 10 15 20 OUTPUT VOLTAGE STEP SIZE (V) Figure 52. Settling Time vs. Step Size (G = 1) ±15 V, VREF = 0 V 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 55. Differential Output Configuration: Gain vs. Frequency 100 100 90 80 70 .001% SETTLED TO 0 SETTLED TO 0.01% CMROUT = 20 log VDIFF_OUT ME LIMITED BY ASUREMENT SYSTEM VCM_OUT 60 50 40 30 20 10 0 10 1 1 10 100 1000 GAIN (V/V) 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 53. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V Figure 56. Differential Output Configuration: Common-Mode Output vs. Frequency Figure 54 Channel Separation vs. Frequency, RL = 2 kΩ, Source Channel at G = 1 Rev. PrB | Page 19 of 27 |
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