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AD8387JSVZ Datasheet(PDF) 3 Page - Analog Devices |
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AD8387JSVZ Datasheet(HTML) 3 Page - Analog Devices |
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3 / 16 page  AD8387 Rev. 0 | Page 3 of 16 SPECIFICATIONS TA = 25°C, AVCC = 15.5 V, DVCC = 3.3 V, VRH = 9.5 V, VRL = 7 V, TA MIN = 0°C, TA MAX = 75°C still air, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit VIDEO DC PERFORMANCE1 TA MIN to TA MAX ,VFS = 5 V VDE—Differential Error Voltage @ DAC code 0 −5.5 −0.8 +5.0 mV @ DAC code 1024 −4.4 −0.5 +3.6 mV @ DAC code 2048 −3.6 −0.3 +3.3 mV @ DAC code 3072 −2.8 −0.3 +2.8 mV @ DAC code 4095 −2.1 +0.2 +2.1 mV DAC code range 0 to 4095 −6.0 +6.0 mV VCME—Common-Mode Error Voltage @ DAC code 0 −2.5 −0.3 +2.5 mV @ DAC code 1024 −2.5 −0.3 +2.5 mV @ DAC code 2048 −2.5 −0.3 +2.5 mV @ DAC code 3072 −2.5 −0.3 +2.5 mV @ DAC code 4095 −2.5 −0.3 +2.5 mV DAC code range 0 to 4095 −3.5 +3.5 mV ΔVDE—VDE Channel Matching @ DAC code 0 1.9 4.8 mV @ DAC code 1024 1.8 4.3 mV @ DAC code 2048 1.6 4.0 mV @ DAC code 3072 1.4 3.8 mV @ DAC code 4095 1.0 2.8 mV DAC code range 0 to 4095 5.5 mV ΔV—Channel Matching @ DAC code 0 2.7 mV @ DAC code 1024 2.7 mV @ DAC code 2048 2.5 mV @ DAC code 3072 2.5 mV @ DAC code 4095 2.0 mV DAC code range 0 to 4095 7.5 mV DNL2 −1 −0.2 LSB VIDEO OUTPUT DYNAMIC PERFORMANCE TA MIN to TA MAX Data Switching Settling Time to 0.25% VIDx = 5 V step, CL = 150 pF 35 50 ns Data Switching Settling Time to 1% 22 28 ns Data Switching Slew Rate 20% to 80% 420 V/μs CLK and Data Feedthrough3 15 mV p-p All-Hostile Crosstalk4 Amplitude 69 mV p-p Glitch Duration 50 ns DAC Transition Glitch Energy DAC Code 2047 to 2048 0.4 nV-s Invert Switching Settling Time to 0.25% VIDx = 10 V step, CL = 150 pF 70 150 ns Invert Switching Settling Time to 1% 34 40 ns Invert Switching Slew Rate 20% to 80% 700 V/μs Invert Switching Overshoot 25 mV |
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