NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
REV 1.0
May, 2001
21
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered
when CS , RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to pre-
charge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which
bank(s) is to be precharged when the command is issued.
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a
delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is
known as tDPL, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be
executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Pre-
charge time (tRP).
Burst Write with Auto-Precharge Interrupted by Read
Bank Selection for Precharge by Address Bits
A10
Bank Select
Precharged Bank(s)
LOW
BA0, BA1
Single bank defined by BA0, BA1
HIGH
DON’T CARE
All Banks
DIN A0
COMMAND
NOP
NOP
NOP
WRITE A
Auto-Precharge
DIN A1
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
*
tCK3, DQs
CAS latency = 3
Bank A can be reactivated at completion of tDAL .
*
READ B
DIN A2
NOP
DOUT B 0
DOUT B1
DOUT B 2
tDAL‡
(Burst Length = 4, CAS Latency = 3)
See the Clock Frequency and Latency table.
‡ tDAL is a function of clock cycle time and speed sort.
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