Nexperia

74LVC06A

Hex inverter with open-drain outputs

12. Abbreviations

Table 10. Abbreviations

Acronym

Description

CDM

Charged Device Model

CMOS

Complementary Metal-Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

Change notice Supersedes

74LVC06A v.7

20200804

Product data sheet

-

74LVC06A v.6

Modifications:

• The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4: Derating values for Ptot total power dissipation updated.

• Package outline drawing Fig. 10 (DHVQFN14) updated.

74LVC06A v.6

20111110

Product data sheet

-

74LVC06A v.5

Modifications:

• Table 6: Conditions column, additional supply current VCC range updated

74LVC06A v.5

20111024

Product data sheet

-

74LVC06A v.4

Modifications:

• Table 7: values added for lower voltage ranges

74LVC06A v.4

20110810

Product data sheet

-

74LVC06A v.3

Modifications:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4, Table 5, Table 6, Table 7, and Table 9: values added for lower voltage ranges.

74LVC06A v.3

20031127

Product specification

-

74LVC06A v.2

74LVC06A v.2

20030828

Product specification

-

74LVC06A v.1

74LVC06A v.1

20000307

Product specification

-

-

74LVC06A

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2020. All rights reserved

Product data sheet

Rev. 7 — 4 August 2020

10 / 12