 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
GWIXP420BBT Datasheet(PDF) 35 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
GWIXP420BBT Datasheet(HTML) 35 Page - Intel Corporation |
|
|
35 / 134 page  Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet March 2005 Document Number: 252479, Revision: 005 35 SDM_CKE Z 1 O SDRAM Clock Enable: CKE is driving high to activate the clock to an external SDRAM and driven low to de-activate the CLK to an external SDRAM. SDM_DQM[3:0] Z 0 O SDRAM Data bus mask: DQM is used to byte select data during read/write access to an external SDRAM. Table 6. SDRAM Interface (Sheet 2 of 2) Name Power on Reset1 Reset2 Type† Description 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † For a legend of the Type codes, see Table 5 on page 33. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
