| Electronic Components Datasheet Search |
|
GWIXC1100BCT Datasheet(PDF) 98 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
GWIXC1100BCT Datasheet(HTML) 98 Page - Intel Corporation |
|
98 / 134 page ![]() Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor March 2005 Datasheet 98 Document Number: 252479, Revision: 005 5.5.2.4 MII Figure 20. MII Output Timings Table 48. MII Output Timings Values Symbol Parameter Min. Max. Units Notes T1 Clock to output delay for ETH_TXDATA and ETH_TXEN. 017 ns 1 T2 ETH_TXDATA and ETH_TXEN hold time after ETH_TXCLK. 2 ns Note: 1. These values satisfy the MII specification requirement of 0 ns to 25 ns clock to output delay. Figure 21. MII Input Timings Table 49. MII Input Timings Values Symbol Parameter Min. Max. Units Notes T3 ETH_RXDATA and ETH_RXDV setup time prior to rising edge of ETH_RXCLK 5.5 ns 1, 2 T4 ETH_RXDATA and ETH_RXDV hold time after the rising edge of ETH_RXCLK 0 ns 1, 2, 3 Notes: 1. These values satisfy the MII specification requirement of 10-ns setup and hold time. 2. Timing tests were performed with a 70-pF capacitor to ground. 3. This parameter has been simulated but has not been fully tested. A9580-01 eth_tx_clk eth_tx_data[7:0] eth_tx_en eth_crs T1 T2 A9581-01 eth_rx_clk eth_rx_data[7:0] eth_rx_dv eth_crs T4 T3 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |