COM20020D datasheet(52/72 Pages) SMSC

52 / 72 page

TIMING DIAGRAMS

FIGURE 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE

AD0-AD2,

VALID

nCS

ALE

VALID DATA

t2,

D3-D7

DIR

t10

nDS

t11

t12

t13

t14

Note 2

Parameter

min

max

units

t10

t11

t12

t13

t14

Address Setup to ALE Low

Address Hold from ALE Low

nCS Setup to ALE Low

nCS Hold from ALE Low

ALE Low to nDS Low

nDS Low to Valid Data

nDS High to Data High Impedance

Cycle Time (nDS Low to Next Time Low)

DIR Setup to nDS Active

DIR Hold from nDS Inactive

ALE High Width

ALE Low Width

nDS Low Width

nDS High Width

4TARB

MUST BE: RBUSTMG bit = 0

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

Note 2:

Read cycle for Address Pointer Low/High Registers occurring after an access

to Data Register requires a minimum of 5TARB from the trailing edge of nDS to

the leading edge of the next nDS.

COM20020D Datasheet(PDF) 52 Page - SMSC Corporation

COM20020D Datasheet(HTML) 52 Page - SMSC Corporation

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