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VSC835 Datasheet(PDF) 4 Page - Vitesse Semiconductor Corporation |
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VSC835 Datasheet(HTML) 4 Page - Vitesse Semiconductor Corporation |
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4 / 18 page ![]() VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 7/24/00 G52270-0, Rev. 4.1 If any change in a monitor state occurs after sampling by MONCLK, an interrupt will be signalled by asserting INTB, and the user must identify the offending channel by reading the monitor states. The interrupt will be cleared when the corresponding activity monitor is read, but the monitor state will not be changed. If multiple monitors have triggered the interrupt, it will persist until all the corresponding monitors have been read. LOA requires a minimum signal level of 30-150mV peak-peak to recognize an input as active. This is required to distinguish noise on an unconnected signal (where both inputs float to the termination voltage) from activity on a live signal. A minimum of two transitions defines activity. The threshold signal level is controlled by the voltage on the VHYS pin. In order to keep the hysteresis in a useful range, it is recommended that VHYS be nominally tied to VCC (useful range is 2.0V to VCC ). . AC Characteristics note: Unless otherwise stated, all specifications are guaranteed but not tested. note 1: Skew between any two input channels to a given output. note 2: Skew between any two output channels from the same input channel. note 3: Required for high-speed output rise/fall spec at FRATE=2.5 Gbits/s. For lower rate signals, use 0.375/FRATE note 4: Broadband jitter added to a jitter-free signal; jitter is primarily in the form of ISI for random data Table 2: Memory Map Address Access Description 00h R/W Output Y0’s programmed input channel (write and then assert CONFIG to program) 01h R/W Output Y1’s programmed input channel ... ... ... 21h R/W Output Y33’s programmed input channel 22h, 23h R/O Rx Signal monitor for inputs [A0-A3], [A4-A7] (Logic ‘1’=No activity) 24h, 25h R/O Rx Signal monitor for inputs [A8-A11], [A12-A15] 26h, 27h R/O Rx Signal monitor for inputs [A16-A19], [A20-A23] 28h, 29h R/O Rx Signal monitor for inputs [A24-A27], [A28-A31] 2Ah R/O Rx Signal monitor for inputs [A32-A33] Table 3: Data Path Parameter Description Min Typ Max Units FRATE Data rate - - 2.5 Gbits/s TISKW Input channel delay skew (1) - 300 - ps TOSKW Output channel delay skew (2) - 300 - ps tR, tF High-speed input rise/fall times, 20% to 80% (3) - - 150 ps tR, tF High-speed output rise/fall times, 20% to 80% - - 150 ps tjP Output data eye jitter, peak-peak, 231 PRBS (4) - - 100 ps |
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