MP86952

– 70A INTELLI-PHASE™ SOLUTION WITH BUILT-IN MOSFETS AND DRIVERS

MP86952 Rev. 1.0

MonolithicPower.com

3

5/13/2021

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PIN FUNCTIONS

Pin #

Name

Description

1, 6, 31,

37, 39, 41

NC

No connection.

2

AGND

Analog ground.

3

VDD

Supply voltage (3.3V) for the internal circuitry. Connect the VDD and VDRV pins

with a

2.2Ω resistor. Decouple VDD with a 1µF of greater ceramic capacitor

connected to AGND. Connect AGND and PGND at the VDD capacitor

’s ground

connection.

4

VDRV

Driver voltage. Connect the VDRV pin to the 3.3V supply. Decouple VDRV with a

1µF to 4.7µF ceramic capacitor.

5, 7, 8, 9,

20, 21, 22, 23,

24, 40

PGND

Power ground.

10, 11, 12, 13,

14, 15, 16, 17,

18, 19

SW

Phase node.

25, 26, 27, 28,

29, 30

VIN

Input supply voltage. Place a ceramic input capacitor (CIN) close to the device to

support the switching current and minimize parasitic inductance.

32

PHASE

Switching node for the bootstrap capacitor connection.

33

BST

Bootstrap. The BST pin requires a 0.1µF to 0.22µF capacitor to drive the power

MOSFET’s gate above the supply voltage. Connect BST to the capacitor between

SW and BST to form a floating supply across the MOSFET driver.

34

PWM

Pulse-width modulation input. Float the PWM pin or drive PWM to a middle state

to put SW in a high-impedance (Hi-Z) state.

35

EN

Enable. Pull the EN pin low to disable the device and put SW in a Hi-Z state.

36

TOUT/FLT

Single-pin temperature sense and fault reporting. If a fault occurs, the

TOUT/FLT pin is pulled up to VDD

’s voltage level.

38

IOUT

Current-sense output. Use an external resistor to adjust the voltage to be

proportional to the inductor current (IL).

ABSOLUTE MAXIMUM RATINGS (1)

Supply voltage (VIN) ..................................... 18V

VIN to VPHASE (DC) .........................-0.3V to +25V

VIN to VPHASE (10ns) ..........................-5V to +32V

VSW to PGND (DC)................ -0.3V to VIN + 0.3V

VSW to PGND (25ns) ........................-5V to +25V

VBST .................................................. VPHASE + 4V

VDD, VDRV .........................................-0.3V to +4V

All other pins ........................ -0.3V to VDD + 0.3V

Instantaneous current ............................... 125A

Junction temperature ................................150°C

Lead temperature .....................................260°C

Storage temperature ................ -65°C to +150°C

ESD Ratings

Human body model (HBM) .................. Class 1C

Charged device model (CDM) ...........Class C2B

Recommended Operating Conditions (2)

Supply voltage (VIN) ............................ 3V to 16V

Driver voltage (VDRV).......................... 3V to 3.6V

Logic voltage (VDD) ............................ 3V to 3.6V

Operating junction temp (TJ)…. -40°C to +125°C

Thermal Resistance (3) (4)

θJB θJC_TOP

LGA-41 (5mmx6mm) ........... 2.2...... 8.7.... °C/W

Notes:

1) Exceeding these ratings may damage the device.

2) The device is not guaranteed to function outside of its

operating conditions.

3)

θ

JB is the thermal resistance from the junction to the board

around the PGND soldering point.

4)

θ

JC_TOP is the thermal resistance from the junction to the top of

the package.