ZSSC1750 datasheet(23/117 Pages) RENESAS

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ZSSC1750 / ZSSC1751 Datasheet

April 20, 2016

2.2.1

Digital I/Os

The digital I/O pins include the SPI interface pins, MCU clock, rest and interrupt pins, LIN UART pins (for

ZSSC1750 only), and watchdog timer disable pin.

All digital input pins of the ZSSC1750/51 feature a Schmitt trigger (see Figure 2.2-B), as well as configurable

pull-down resistors and protection diodes. The pull-down resistors have values specified by parameter 1.3.16.

They are enabled after power-on-reset and can be further controlled via the pullResEna register (see section

3.11.1.1).

All digital output pins of the ZSSC1750/51 have a push-pull stage and protection diodes connected as shown in

Figure 2.2-C.

All digital I/Os are supplied by the VDDP voltage, which is switched off when the ZSSC1750/51 is in the ULP or

OFF State (see section 2.3); i.e. the I/Os are also off in this state.

Note: In order to avoid parasitic supply of the digital I/O circuitry when the ZSSC1750/51 is in the ULP or OFF

State, the digital outputs of the external microcontroller should be disabled. This is valid when the external micro-

controller is not supplied by the ZSSC1750/51.

2.2.2

External Microcontroller (MCU) Supply Pins

The ZSSC1750/51 provides two separate regulators for the external microcontroller supply. The VDDP regulator

provides 3.3V, and VDDC provides 1.8V. Both voltages are switched off when the ZSSC1750/51 is in the ULP or

OFF State. For more information regarding the VDDP and VDDC regulators, including trimming options, refer to

sections 3.12.5 and 3.12.6. The current capability of the VDDP and VDDC pins is specified by parameters 1.3.11

and 1.3.13 respectively.

2.2.3

SLEEPN Power State Indicator Pin

The ZSSC1750/51 features a SLEEPN pin that indicates the power state of the ZSSC1750/51 (see section 2.3).

When the ZSSC1750/51 is in the full power (FP) state or low power (LP) state, the SLEEPN pin is HIGH; when

the state is ULP or OFF, SLEEPN is LOW. In order to remain powered in these states, the SLEEPN pin circuitry

is supplied by the VDDL regulator. When HIGH, the SLEEPN pin has a 1.8V output voltage level; the HIGH and

LOW levels are specified with parameters 1.3.20 and 1.3.21.

In the application, the SLEEPN pin can be connected to the external microcontroller (if it remains powered in

system Sleep Mode), or it can be used for disabling an external circuitry when the ZSSC1750/51 goes into one

of the power saving modes. Depending on the application specifics, an external buffer (e.g., a transistor) might

be needed for the SLEEPN pin for a proper level or current conditioning.

ZSSC1750 Datasheet(PDF) 23 Page - Renesas Technology Corp