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PUSB3BB2DF Datasheet(PDF) 10 Page - Nexperia B.V. All rights reserved

Part # PUSB3BB2DF
Description  Extremely low clamping low capacitance ESD protection
PDF  15 Pages
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Manufacturer  NEXPERIA [Nexperia B.V. All rights reserved]
Direct Link  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved

PUSB3BB2DF Datasheet(HTML) 10 Page - Nexperia B.V. All rights reserved

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Nexperia
PUSB3BB2DF
Extremely low clamping low capacitance ESD protection
VCL (V)
0
8
6
2
4
aaa-030889
4
2
6
8
IPP
(A)
0
IEC 61000-4-5; tp = 8/20 µs; positive pulse
Fig. 18. Dynamic resistance with positive clamping;
typical values
VCL (V)
-8
0
-2
-6
-4
aaa-030890
-4
-6
-2
0
IPP
(A)
-8
IEC 61000-4-5; tp = 8/20 µs; negative pulse
Fig. 19. Dynamic resistance with negative clamping;
typical values
10. Application information
The device is designed for the protection of two signal lines from surge pulses and ESD damage.
The device is suitable on lines where the signal polarities are both, positive and negative with
respect to ground.
The device uses an advanced clamping structure showing a negative dynamic resistance. This
snap-back behavior strongly reduces the clamping voltage system behind the ESD protection
during an ESD event. Do not connect unlimited DC current sources to the data lines to avoid
keeping the ESD protection device snap-back state after exceeding breakdown voltage (due to an
ESD pulse for instance).
aaa-030287
ESD protection diode
GND
lines to be protected
Fig. 20. Application diagram
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge
transients. The following guidelines are recommended:
1. Place the device as close to the input terminal or connector as possible.
2. Minimize the path length between the device and the protected line.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Use ground planes whenever possible. For multilayer PCBs, use ground vias.
PUSB3BB2DF
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2020. All rights reserved
Product data sheet
3 November 2020
10 / 15



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