NB650/NB650H

– 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS

NB650/NB650H Rev. 1.13

www.MonolithicPower.com

15

10/7/2019

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Preliminary Specifications Subject to Change

© 2019 MPS. All Rights Reserved.

)

V

2

1

V

(V

R1

1

V

2

1

V

R2A

RAMP

REF

OUT1

RAMP

REF











(23)

R2A

1

V

2

1

V

)

V

2

1

V

(V

R1

1

1

R2B

RAMP

REF

RAMP

REF

OUT2













(24)

R2A

1

V

2

1

V

)

V

2

1

V

(V

R1

1

1

R2C

RAMP

REF

RAMP

REF

OUT3













(25)

Select CDC>10×C4 for better DC blocking, but

select a value less than 0.47µF when considering

start up performance. For larger CDC values for

better FB noise immunity, combine with reduced

R1 and R2 to limit the CDC to a reasonable value

without affecting system start-up. Note that even

with CDC, the load and line regulation are still

related to VRAMP.

R1

R2

Ceramic

SW

FB

Vo

L

Cdc

R4

C4

Figure 11: Simplified Circuit with Ceramic DC-

Blocking Capacitor

Input Capacitor

The input current to the step-down converter is

discontinuous, and therefore requires a capacitor

to supply the AC current to the step-down

converter while maintaining the DC input voltage.

Use ceramic capacitors for best performance.

The

capacitance

varies

significantly

over

temperature. Capacitors with X5R and X7R

ceramic dielectrics are recommended because

they are fairly stable over temperature.

In the layout, place the input capacitors as close

to the IN pin as possible.

The capacitors must also have a ripple current

rating greater than the maximum input ripple

current of the converter. The input ripple current

can be estimated as:

OUT

OUT

CIN

OUT

IN

IN

VV

I

I

(1

)

VV





 

(26)

The worst-case condition occurs at:

OUT

CIN

I

I

2



(27)

For simplification, choose an input capacitor

whose RMS current rating is greater than half of

the maximum load current.

The input capacitance value determines the input

voltage ripple of the converter. If the system

requires a specific input voltage ripple, choose

the input capacitor that meets the specification.

The input voltage ripple can be estimated as:

OUT

OUT

OUT

IN

SW

IN

IN

IN

I

V

V

V

(1

)

f

C

V

V







 



(28)

The worst-case condition occurs at VIN = 2VOUT,

where:

OUT

IN

SW

IN

I

1

V

4

f

C



 



(29)

Output Capacitor

The output capacitor maintains the DC output

voltage. Use ceramic or POSCAP capacitors.

The output voltage ripple can be estimated as:

OUT

OUT

OUT

ESR

SW

IN

SW

OUT

VV

1

V

(1

) (R

)

f

L

V

8 f

C





 











(30)

Where RESR is the equivalent series resistance

(ESR) of the output capacitor.

For

ceramic

capacitors,

the

capacitance

dominates

the

impedance

at

the

switching

frequency, and causes the majority of the output

voltage ripple. For simplification, the output

voltage ripple can be estimated as:

OUT

OUT

OUT

2

IN

SW

OUT

VV

V

(1

)

V

8 f

L C





 



 

(31)

The output voltage ripple caused by ESR is very

small, and therefore requires an external ramp to

stabilize the system. The external ramp can be

generated through resistor R4 and capacitor C4

following equations 5, 9 and 10.

For POSCAP capacitors, the ESR dominates the

impedance at the switching frequency. The ramp

voltage generated from the ESR is high enough

to stabilize the system. Therefore, an external

ramp is not needed. A minimum ESR value of