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AD9549 Datasheet(PDF) 13 Page - Analog Devices

Part # AD9549
Description  Dual Input Network Clock Generator/Synchronizer
PDF  78 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9549 Datasheet(HTML) 13 Page - Analog Devices

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Preliminary Technical Data
AD9549
Rev. PrA | Page 13 of 78
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted: AVDD, AVDD3, and DVDD at nominal supply voltage; fS= 1 GHz, DAC RSET= 10kΩ.
Plot 1: Additive Phase Noise at HSTL Output Driver. Sysclk=1 GHz
(SysClk PLL Bypassed). Ref=19.44 MHz., Fout=311.04 MHz.
DPLL loop BW= 1 kHz.
Plot 2: Additive Phase Noise at HSTL Output Driver. Sysclk=1 GHz
(SysClk PLL Bypassed). Ref=19.44 MHz., Fout=622.08 MHz, DPLL
loop BW= 1 kHz. HSTL Output Doubler Enabled



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