WM8580 datasheet(44/92 Pages) WOLFSON

44 / 92 page

WM8580

Production Data

PD Rev 4.0 February 2007

SECONDARY AUDIO INTERFACES (SAIF RX AND SAIF TX)

The Transmit and Receive sides of the Secondary Audio Interface share a common LRCLK and a

common BCLK. These can be supplied externally (slave mode) or they can be generated internally

by the WM8580 (master mode). The master mode LRCLK/BCLK are created by the Master Mode

Clock Gen module. The control of this module is described on page 21.

The clock supplied to this module can be ADCMCLK, PLLACLK, PLLBCLK, or MCLK and is selected

using the SAIFMS_CLKSEL register. If the digital routing has been configured such that the SAIF

Transmitter is sourcing the S/PDIF Receiver, then PLLACLK is automatically selected, and it is

recommended that the interface operate in master mode. However, if the SAIF Transmitter sources

something other than the S/PDIF Receiver, and the S/PDIF Receiver is powered up, the PLLACLK

and PLLBCLK are invalid for SAIF operation, so the choice is limited to ADCMCLK (default) or

MCLK.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R11

SAIF 1

0Bh

7:6

SAIFMS_

CLKSEL

SAIF Master Mode clock source

00 = ADCMCLK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

Table 37 SAIF Master Mode Clock Control

Figure 31 SAIF Clock Selection

WM8580 Datasheet(PDF) 44 Page - Wolfson Microelectronics plc