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WM8580 Datasheet(PDF) 63 Page - Wolfson Microelectronics plc

Part # WM8580
Description  Multichannel CODEC with S/PDIF Transceiver
PDF  92 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8580 Datasheet(HTML) 63 Page - Wolfson Microelectronics plc

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Production Data
WM8580
w
PD Rev 4.0 February 2007
63
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0
AUDIO_N
-
Recovered Channel Status bit-1.
0 = Data word represents audio PCM samples.
1 = Data word does not represent audio PCM samples.
1
PCM_N
-
Indicates that non-audio code (defined in IEC-61937)
has been detected.
0 = Sync code not detected.
1 = Sync code detected – received data is not audio
PCM.
2
CPY_N
-
Recovered Channel Status bit-2 (active low).
0 = Copyright is asserted for this data.
1 = Copyright is not asserted for this data.
3
DEEMPH
-
Recovered Channel Status bit-3
0 = Recovered S/PDIF data has no pre-emphasis.
1 = Recovered S/PDIF data has pre-emphasis
5:4
REC_FREQ
[1:0]
--
Indicates recovered S/PDIF clock frequency:
00 = 192kHz
01 = 96kHz / 88.2kHz
10 = 48kHz / 44.1kHz
11 = 32kHz
R49
SPDSTAT
31h
(read-only)
6
UNLOCK
-
Indicates that the S/PDIF Clock Recovery circuit is
unlocked or that the input S/PDIF signal is not present.
0 = Locked onto incoming S/PDIF stream.
1 = Not locked to the incoming S/PDIF stream or the
incoming S/PDIF stream is not present.
Table 62 S/PDIF Status Register
The interrupt and update signals used to generate INTB can be masked as necessary. The MASK
register bit prevents flags from asserting INTB and from updating the Interrupt Status Register (R43).
Masked flags update the S/PDIF Status Register (R49).
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R37
INTMASK
25h
8:0
MASK[8:0]
000000000
When a flag is masked, it does not update the Interrupt
Status Register or assert INTB.
0 = unmask, 1 = mask.
MASK[0] = mask control for UPD_UNLOCK
MASK[1] = mask control for INT_INVALID
MASK[2] = mask control for INT_CSUD
MASK[3] = mask control for INT_TRANS_ERR
MASK[4] = mask control for UPD_AUDIO_N
MASK[5] = mask control for UPD_PCM_N
MASK[6] = mask control for UPD_CPY_N
MASK[7] = mask control for UPD_DEEMPH
MASK[8] = mask control for UPD_REC_FREQ
Table 63 Interrupt Mask Control Register



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