WM9714LGEFLSLASHV datasheet(65/94 Pages) WOLFSON

65 / 94 page

Pre-Production

WM9714L

PP Rev 3.0 June 2006

POWER MANAGEMENT

INTRODUCTION

The WM9714L includes the standard power down control register defined by the AC’97 specification

(register 26h). Additionally, it also allows more specific control over the individual blocks of the device

through register Powerdown registers 3Ch and 3Eh. Each particular circuit block is active when both

the relevant bit in register 26h AND the relevant bit in the Powerdown registers 3Ch and 3Eh are set

to ‘0’.

Note that the default power-up condition is all OFF.

AC97 CONTROL REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PR6

1 (OFF)

Disables all output PGAS

PR5

1 (OFF)

Disables internal clock

PR4

1 (OFF)

Disables AC-link interface (external clock off)

PR3

1 (OFF)

Disables VREF, input PGAs, DACs, ADCs,

mixers and outputs

PR2

1 (OFF)

Disables input PGAs and mixers

PR1

1 (OFF)

Disables stereo DAC

PR0

1 (OFF)

Disables stereo ADCs and record mux PGA

REF

Read-only bit, indicates VREF is ready (inverse

of PR3)

ANL

Read-only bit, indicates analogue mixers are

ready (inverse of PR2)

DAC

Read-only bit, indicates stereo DAC is ready

(inverse of PR1)

26h

Powerdown/

Status

ADC

Read-only bit, indicates stereo ADC is ready

(inverse of PR0)

Table 59 Powerdown and Status Register (Conforms to AC’97 Rev 2.2)

EXTENDED POWERDOWN REGISTERS

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PADCPD

1 (OFF)

Disables AUXADC

VMID1M

1 (OFF)

Disables 1Meg Vmid resistor string

TSHUT

1 (OFF)

Disables thermal shutdown

VXDAC

1 (OFF)

Disables VXDAC

AUXDAC

1 (OFF)

Disables AUXDAC

VREF

1 (OFF)

Disables master bias reference generator

PLL

1 (OFF)

Disables PLL

DACL

1 (OFF)

Disables left DAC (see Note 1)

DACR

1 (OFF)

Disables right DAC (see Note 1)

ADCL

1 (OFF)

Disables left ADC

ADCR

1 (OFF)

Disables right ADC

HPLX

1 (OFF)

Disables left headphone mixer

HPRX

1 (OFF)

Disables right headphone mixer

SPKX

1 (OFF)

Disables speaker mixer

3Ch

Powerdown

(1)

1 (OFF)

Disables mono mixer

Note: When analogue inputs or outputs are disabled, they are internally connected to VREF

through a large resistor (VREF=AVDD/2 except when VREF and VMID1M are both OFF). This

maintains the potential at that node and helps to eliminate pops when the pins are re-enabled.

Table 60 Extended Power Down Register (1) (Additional to AC’97 Rev 2.2)

Note:

When disabling a PGA, always ensure that it is muted first.

WM9714LGEFL/V Datasheet(PDF) 65 Page - Wolfson Microelectronics plc

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