AD82587D datasheet(17/45 Pages) ESMT

17 / 45 page

ESMT

AD82587D

Elite Semiconductor Memory Technology Inc.

Publication Date: Jan. 2018

Revision: 1.6

17/45

Operation Description

 Reset

When the RESET pin is lowered, AD82587D will clear the stored data and reset the register table to

default values. AD82587D will exit reset state at the 256

th MCLK cycle after the RESET pin is raised to

high.

 Power down control

AD82587D has a built-in volume fade-in/fade-out design for PD/Mute function. The relative PD timing

diagrams for loudspeakers are shown below.

Volume Level

time

+24 dB

-103 dB

Fade out

time

Fade in

time

Mute

state

PD enabled

PD disabled

Original level

Volume Level

time

+24 dB

-103 dB

Fade out

time

Fade in

time

PD enabled

PD disabled

Original level

)

(

512

)

(

)

(

)

(

arg

or iginal



The volume level will be decreased to -∞dB in several LRCIN cycles. Once the fade-out procedure is

finished, AD82587D will turn off the power stages, clock signals (for digital circuits) and current (for analog

circuits). After PD pin is pulled low, AD82587D requires Tfade to finish the forementioned work before

entering power down state. Users can not program AD82587D during power down state. Also, all settings in

the registers will remain intact unless DVDD is removed.

If the PD signal is removed during the fade-out procedure (above, right figure), AD82587D will still execute

the fade-in procedure. In addition, AD82587D will establish the analog circuits

’ bias current and send the

clock signals to digital circuits. Afterwards, AD82587D will return to its normal status.

AD82587D Datasheet(PDF) 17 Page - Elite Semiconductor Memory Technology Inc.

AD82587D Datasheet(HTML) 17 Page - Elite Semiconductor Memory Technology Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL