AT90S2313 datasheet(34/92 Pages) ATMEL

34 / 92 page

AT90S2313

0839I–AVR–06/02

The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read

and write access. If Timer/Counter1 is written to and a clock source is selected, the

Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-

ten value.

Timer/Counter1 Output

Compare Register A –

OCR1AH and OCR1AL

The Output Compare Register is a 16-bit read/write register.

The Timer/Counter1 Output Compare Register contains the data to be continuously

compared with Timer/Counter1. Actions on compare matches are specified in the

Timer/Counter1 Control and Status Registers.

Since the Output Compare Register (OCR1A) is a 16-bit register, a temporary register

TEMP is used when OCR1A is written to ensure that both bytes are updated simulta-

neously. When the CPU writes the high byte, OCR1AH, the data is temporarily stored in

the TEMP Register. When the CPU writes the low byte, OCR1AL, the TEMP Register is

simultaneously written to OCR1AH. Consequently, the high byte OCR1AH must be writ-

ten first for a full 16-bit register write operation.

The TEMP Register is also used when accessing TCNT1, and ICR1. If the main pro-

gram and interrupt routines perform access to registers using TEMP, interrupts must be

disabled during access from the main program or interrupts if interrupts are re-enabled.

Timer/Counter1 Input Capture

The Input Capture Register is a 16-bit read-only register.

When the rising or falling edge (according to the input capture edge setting [ICES1]) of

the signal at the input capture pin (ICP) is detected, the current value of the

Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time,

the Input Capture Flag (ICF1) is set (one).

Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register TEMP

is used when ICR1 is read to ensure that both bytes are read simultaneously. When the

CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte

ICR1H is placed in the TEMP Register. When the CPU reads the data in the high byte

ICR1H, the CPU receives the data in the TEMP Register. Consequently, the low byte

ICR1L must be accessed first for a full 16-bit register read operation.

Bit

15141312

1110

$2B ($4B)

MSB

OCR1AH

$2A ($4A)

LSB

OCR1AL

76543

210

Read/Write

R/W

Initial value

00000

000

00000

000

Bit

15141312

1110

$25 ($45)

MSB

ICR1H

$24 ($44)

LSB

ICR1L

76543

210

Read/Write

RRRRRR

Initial value

00000

000

00000

000

AT90S2313 Datasheet(PDF) 34 Page - ATMEL Corporation

AT90S2313 Datasheet(HTML) 34 Page - ATMEL Corporation

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