ATMEGA3250 datasheet(55/353 Pages) ATMEL

55 / 353 page

ATmega325/3250/645/6450

2570J–AVR–11/06

EIMSK – External Interrupt

Mask Register

• Bit 7 – PCIE3: Pin Change Interrupt Enable 3

When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 3 is enabled. Any change on any enabled PCINT30..24 pin will

cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-

cuted from the PCINT3 Interrupt Vector. PCINT30..24 pins are enabled individually by

the PCMSK3 Register.

This bit is reserved bit in ATmega325/645 and should always be written to zero.

• Bit 6 – PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will

cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-

cuted from the PCINT2 Interrupt Vector. PCINT23..16 pins are enabled individually by

the PCMSK2 Register.

This bit is reserved bit in ATmega325/645 and should always be written to zero.

• Bit 5 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will

cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-

cuted from the PCINT1 Interrupt Vector. PCINT15..8 pins are enabled individually by the

PCMSK1 Register.

• Bit 4 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause

an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed

from the PCINT0 Interrupt Vector. PCINT7..0 pins are enabled individually by the

PCMSK0 Register.

• Bit 0 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and

ISC00) in the External Interrupt Control Register A (EICRA) define whether the external

interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity

on the pin will cause an interrupt request even if INT0 is configured as an output. The

corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Inter-

rupt Vector.

Bit

654

0x1D (0x3D)

PCIE3

PCIE2

PCIE1

PCIE0

–

–INT0

EIMSK

Read/Write

R/W

Initial Value

ATMEGA3250 Datasheet(PDF) 55 Page - ATMEL Corporation

ATMEGA3250 Datasheet(HTML) 55 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL