56F803 datasheet(42/57 Pages) FREESCALE

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Serial Peripheral Interface (SPI) Timing

56F803 Technical Data, Rev. 16

Freescale Semiconductor

Figure 3-18 SPI Master Timing (CPHA = 0)

Data Valid for outputs

Master

Slave (after enable edge)

tDV

—

4.5

20.4

Figures 3-18, ,

3-20, 3-21

Data invalid

Master

Slave

tDI

—

Figures 3-18, ,

3-20, 3-21

Rise time

Master

Slave

—

11.5

10.0

Figures 3-18, ,

3-20, 3-21

Fall time

Master

Slave

—

9.7

9.0

Figures 3-18, ,

3-20, 3-21

Parameters listed are guaranteed by design.

Table 3-12 SPI Timing1

Operating Conditions: V

SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz

Characteristic

Symbol

Min

Max

Unit

See Figure

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

MSB in

Bits 14–1

LSB in

Master MSB out

Bits 14–1

Master LSB out

(Input)

SS is held High on master

tDI

tDS

tDI(ref)

tDV

tCH

tDH

tCL

tCH

tCL

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