CX20921 AudioSmart Data Sheet

Reset (Active Low)

Conexant Confidential

03/11/15

001DSR01

15

Reset (Active Low)

During initial power-up, the external reset should be held low for a minimum of 100ms to allow all power

supplies to become stable and for the internal crystal to stabilize. Refer to the customer reference

schematic for Resistor-Capacitor (RC) circuit values and connections.

Serial Peripheral Interface (SPI) Master

The CX20921 offers an SPI master interface that is intended to interface with SPI slave devices, such as

serial flash. The SPI block consists of a TX and an RX First In, First Out (FIFO) that is 8x32 bits with

several registers for control and status. The SPI interface accommodates various controls for clock

polarity, a phase shift of the clock, and slave select polarity.

The SPI clock is derived from the PLL_SPI_CLK and can be programmed by a field in the control register.

Two slave selection signals are available to allow use of two different SPI peripherals (SS0, SS1).

Note:

The SPI_SS1 is multiplexed with UART_CTS, DMIC_DATA, and I2S_TX_DATA_2.

Figure 4: SPI Transmit Timing

Table 6: SPI Interface Signals

Signal Name

I/O

Def

Function

SPI_CLK

O

NA

Maximum of 50MHz.

SPI_MI

I

NA

Master serial data IN.

SPI_MO

O

NA

Master serial data OUT.

SPI_SS0

O

NA

Chip select 0.

SPI_SS1

O

NA

Chip select 1.