www.ti.com

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

SDA

SCL

Start Condition

S

Stop Condition

P

SCL

Master

Transmitter/

Receiver

Slave

Receiver

Slave

Transmitter/

Receiver

Master

Transmitter

Master

Transmitter/

Receiver

Multiplexer

Slave

SDA

PCA9545A

WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006

Figure 4. Bit Transfer

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while

the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is

high is defined as the stop condition (P) (see Figure 5).

Figure 5. Definition of Start and Stop Conditions

A device generating a message is a transmitter; a device receiving a message is the receiver. The device that

controls the message is the master, and the devices that are controlled by the master are the slaves (see

Figure 6).

Figure 6. System Configuration

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is

not limited. Each byte of eight bits is followed by one acknowlege (ACK) bit. The transmitter must release the

SDA line before the receiver can send an ACK bit.

When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master

must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The

device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable

low during the high pulse of the ACK-related clock period (see Figure 7). Setup and hold times must be taken

into account.

8

Submit Documentation Feedback