Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

AM29BDS640G Datasheet(PDF) 50 Page - Advanced Micro Devices

Part # AM29BDS640G
Description  64 Megabit (4 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
PDF  77 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29BDS640G Datasheet(HTML) 50 Page - Advanced Micro Devices

Back Button AM29BDS640G Datasheet HTML 46Page - Advanced Micro Devices AM29BDS640G Datasheet HTML 47Page - Advanced Micro Devices AM29BDS640G Datasheet HTML 48Page - Advanced Micro Devices AM29BDS640G Datasheet HTML 49Page - Advanced Micro Devices AM29BDS640G Datasheet HTML 50Page - Advanced Micro Devices AM29BDS640G Datasheet HTML 51Page - Advanced Micro Devices AM29BDS640G Datasheet HTML 52Page - Advanced Micro Devices AM29BDS640G Datasheet HTML 53Page - Advanced Micro Devices AM29BDS640G Datasheet HTML 54Page - Advanced Micro Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 50 / 77 page
background image
48
Am29BDS640G
25903C2 May 9, 2006
Data
Sheet
AC Characteristics
Synchronous/Burst Read
Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
Parameter
Description
98
(40 MHz)
78
(54 MHz)
93
(40 MHz)
73
(54 MHz) Unit
JEDEC Standard
tIACC
Latency (Even Address in Handshake
Mode)
Max
9587.595
88
ns
Parameter
Description
98, 99
(40 MHz)
78, 79
(54 MHz)
93, 94
(40 MHz)
73, 74
(54 MHz) Unit
JEDEC Standard
tIACC
Latency—(Non-Handshake or Odd
Address in Handshake mode)
Max
120
106
120
106.5
ns
tBACC
Burst Access Time Valid Clock to
Output Delay
Max
2013.520
14
ns
tACS
Address Setup Time to CLK (See Note)
Min
5
ns
tACH
Address Hold Time from CLK (See
Note)
Min
7
ns
tBDH
Data Hold Time from Next Clock Cycle
Max
4
ns
tOE
Output Enable to Output Valid
Max
20
13.5
20
14
ns
tCEZ
Chip Enable to High Z
Max
10
10.5
10.5
ns
tOEZ
Output Enable to High Z
Max
10
10.5
10.5
ns
tCES
CE# Setup Time to CLK
Min
5
ns
tRDYS
RDY Setup Time to CLK
Min
5
4.5
4.5
ns
tRACC
Ready Access Time from CLK
Max
20
13.5
20
14
ns
tAAS
Address Setup Time to AVD# (See
Note)
Min
5
ns
tAAH
Address Hold Time to AVD# (See Note)
Min
7
ns
tCAS
CE# Setup Time to AVD#
Min
0
ns
tAVC
AVD# Low to CLK
Min
5
ns
tAVD
AVD# Pulse
Min
12
ns
tACC
Access Time
Max
70
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com