ADF4382ABCCZ datasheet(25/70 Pages) AD

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Data Sheet

ADF4382A

THEORY OF OPERATION

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Rev. 0 | 25 of 70

Figure 53. VCO Calibration Block

The following calibration timeout bit fields must be programmed for

autocalibration:

►

CAL_VTUNE_TO: At the beginning of the calibration, VTUNE

is precharged to a nominal voltage, which is dependent on the

temperature of operation. CAL_VTUNE_TO sets the precharge

time as follows:

CAL_VTUNE_TO = Ceil

Target VTUNE Calibration Timeout × fPFD2DCLK_DIV1

The largest value capacitor in the loop filter directly affects the

time taken to precharge to VTUNE. Refer to the Calibration Time

Performance Consideration section for more details.

►

CAL_COUNT_TO: CAL_COUNT_TO is the count calibration

timeout. During autocalibration, there are nine band decisions

to be made to select the final band of operation for the selected

frequency. CAL_COUNT_TO is used to program the time taken

for each band decision. This time affects the calibration accura-

cy. Use the following equation to set the decision time of each

band:

CAL_COUNT_TO = Ceil

Target Band Decision Time × fPFD

2DCLK_DIV1×16

►

CAL_VCO_TO: This bit field is used to set the time required for

frequency settling after each band decision. To se this time, use

the following equation:

CAL_VCO_TO = Ceil

Target VCO Frequency Settling Timeout×fPFD

2DCLK_DIV1

To perform a VCO calibration, set up the following several registers

as outlined in the following procedure:

1. Set DCLK_DIV1 and DCLK_MODE to the values listed in Table

19 and record fDIV_RCLK for later use.

2. Calculate and set the minimum required values for

CAL_VTUNE_TO, CAL_VCO_TO, and CAL_COUNT_TO as

per their corresponding formulas previously described in this

section.

3. Set the N_INT, RFOUT_DIV, and R_DIV bits and the

EN_RDBLR bit by programming Register 0x010 last. Any writes

to Register 0x010 start the VCO autocalibration.

4. Monitor the ADC_BUSY bit and FSM_BUSY bit (Register

0x058, Bit 2 and Bit 3, respectively). The calibration is finished

when ADC_BUSY transitions from high to low, followed with

FSM_BUSY transitioning from high to low.

5. After the VCO calibration is complete, disable the calibra-

tion clocks to limit unwanted spurious content by setting

EN_DRCLK = EN_DNCLK = 0.

Table 19. DCLK_DIV1 and DCLK_MODE Setup

fPFD (MHz)

DCLK_DIV1

DCLK_MODE

fDIV_RCLK (MHz)

≤11

fFPD

>11 and ≤160

fFPD/2

>160 and ≤320

fPFD/4

>320

fPFD/8

Total Autocalibration Time

Use each of the calibration timeout values to calculate the total

autocalibration time as follows:

Total Autocalibration Time = Target VTUNE Calibration Timeout +

(2/fDIV_RCLK) + (10 × VTUNE Setting Time) + VCAL Low Time

where:

VTUNE Settling Time =

Target VTUNE Calibration Timeout + (2 ×fDIV_RCLK

fDIV_RCLK= fPFD

2DCLK_DIV1 + DCLK_MODE

VCAL Low Time= 2fDIV_RCLK

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