P90CL301 datasheet(8/92 Pages) PHILIPS

8 / 92 page

1996 Dec 11

Philips Semiconductors

Preliminary speciﬁcation

Low voltage 16-bit microcontroller

P90CL301BFH (C100)

SYSTEM CONTROL

6.1

Memory organization

The maximum external address space of the controller is

16 Mbytes. It can be partitioned into five address spaces.

These address spaces are designated as either User or

Supervisor space and as either Program or Data space or

as interrupt acknowledge.

For slow memories the CPU can be programmed to insert

a number of wait states. This is done via the eight

Chip-select Control Registers CS0N to CS7N; further to

be denoted as CSnN, where n = 0 to 7. The number of

inserted wait states can vary from 0 to 6, or wait states are

inserted until the DTACK is pulled LOW by the external

address decoding circuitry. If DTACK is asserted

continuously, the P90CL301BFH will run without wait

states using bus cycles of three or four clock periods

depending on the state of the FBC bit in the SYSCON

6.1.1

MEMORY MAP

The memory address space is divided as shown in

Table 2; short addressing space with A31 to A15 = 1.

Table 2

Memory address space

ADDRESS (HEX)

DESCRIPTION

0000 0000 to 00FF FFFF

external 16 Mbytes

memory

0100 0000 to 8000 FFFF

not used

8001 0000 to 8001 FFFF

off-chip 64 kbytes on 8051

bus

8002 0000 to FFFF 7FFF

not used

FFFF 8000 to FFFF 8AFF

internal registers

FFFF 8B00 to FFFF 8FFF

not used

FFFF 9000 to FFFF 91FF

internal 512 bytes RAM

FFFF 9200 to FFFF BFFF

not used

FFFF C000 to FFFF C0FF internal 256 bytes

Test-ROM

FFFF C100 to FFFF FFFF not used

6.2

Programmable chip-select

In order to reduce the external components associated

with memory interface, the P90CL301BFH provides

8 programmable chip-selects. A specific chip-select CSBT

provides default reset values to support a bootstrap

operation.

Each chip-select can be programmed with:

• A base address (A23 to A19)

• A memory bank width of 512 kbytes, 1, 2, 4 or 8 Mbytes

memory size

• A number of wait states (0 to 6 states, or wait for

DTACK) to adapt the bus cycle to the memory cycle

time.

Chip-selects can be synchronized with read, write, or both

read and write, either Address strobe or Data strobe. They

can also be programmed to address low byte, high byte or

word.

Each chip-select is controlled by a control register CSnN

(n = 0 to 7). The control registers are described in

Table 3 to 7.

The RESET instruction does not affect the contents of the

CSnN registers.

FFFF 8A0EH). After reset CSBT is programmed with a

block size of 8 Mbytes with:

• A19 to A23 at logic 0

• M19 to M22 at logic 1

• 6 wait states

• read only mode.

The other chip-selects are held HIGH and will be activated

after initialization of their control registers.

When programmed in reduced access mode (read only,

write only, low byte, high byte), the wait states are

generated internally and if there is any access-violation

when the bit WD in the SYSCON register is set to a logic 1

(time-out), the processor will execute a bus error after the

time-out delay.

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