P90CL301 datasheet(3/92 Pages) PHILIPS

3 / 92 page

1996 Dec 11

Philips Semiconductors

Preliminary speciﬁcation

Low voltage 16-bit microcontroller

P90CL301BFH (C100)

FEATURES

• Fully 68000 software compatible

• Static design with 32-bit internal structure

• Power saving modes: Power-down, Standby and Idle

mode

• External clock input: 27 MHz at 2.7 V

• Single supply voltage of 2.7 to 3.6 V; down to 1.8 V for

RAM retention

• 68000 compatible bus interface

• Intel 8051 compatible bus interface

• 16 Mbytes program/data address range

• 8 programmable chip-selects

• Dynamic bus sizing, 16 or 8-bit memory bus port size

• 56 powerful instruction types:

– 5 basic data types, and

– 14 addressing modes

• 7 programmable interrupt inputs:

– a Non-Maskable Interrupt input (NMIN)

– 14 auto-vectored interrupts and 7 interrupt priority

levels

• 24 port pins (multiplexed with other functions)

• 2 UART serial interfaces; an independent baud rate

generator with two programmable outputs (UART0 and

UART1)

• UART queue with maximum 256 bytes

• I2C-bus serial interface 100 kbaud

• 2 timer arrays including:

– two 16-bit reference counters and 8-bit

programmable prescalers

– six 16-bit match/capture registers with equality

comparators

• Watchdog Timer with 21-bit resolution

• Two 8-bit Pulse Width Modulation (PWM) outputs with

8-bit prescaler

• Four 8-bit Analog-to-Digital Converter (ADC) inputs with

Power-down mode

• 512 bytes RAM on-chip

• On-Circuit Emulation (ONCE) mode and internal

Test-ROM (256 bytes) for on-board testing

• 80-pin LQFP package

• Temperature range −40 to +85 °C

• 0.5 micron CMOS low voltage technology.

DESCRIPTION

The P90CL301BFH is a highly integrated low-voltage

16/32-bit microcontroller especially suitable for digital

mobile systems such as GSM, DCS1900, IS54/95 and

other applications requiring low voltage, low power

consumption and high computing power. It is fully software

compatible with the 68000.

The P90CL301BFH optimizes system cost by providing

both standard as well as advanced peripheral functions

on-chip. The P90CL301BFH has a full static design and

special Idle, Standby and Power-down modes which allow

further reduction of the total system power consumption.

An 80-pin LQFP package dramatically reduces system

size requirements.

2.1

Compatibility between P90CL301AFH and

P90CL301BFH

For functional compatibility between P90CL301AFH

(SAC1 process) and P90CL301BFH (C100 process), the

following points should be considered when using the

P90CL301BFH:

• Wake-up; to wake-up the processor from Power-down

mode via the activation of an external SPn pin, it is

necessary to enable the interrupt mode first by setting

the corresponding bit in the SPCON register.

• SYSCON register; for the P90CL301AFH bits 11 to 15

in the SYSCON register should not be set in order to

keep additional functionality in the P90CL301BFH

inactive.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

TEMPERATURE

RANGE (

°C)

NAME

DESCRIPTION

VERSION

P90CL301BFH

LQFP80

plastic low proﬁle quad ﬂat package; 80 leads;

body 12

× 12 × 1.4 mm

SOT315-1

−40 to +85

P90CL301 Datasheet(PDF) 3 Page - NXP Semiconductors

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