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Left

Left

Right

DSD

Engine

DSDCLK

DSDL

DSDEN

DSDMODE

DSDR

Right

Multi-Bit

Delta-Signma

Modulator

Digital

Decimation

Filter

(Downby2)

6-bits/ch

128f

S

6-bits/ch

64f

S

MULTI-BIT MODULATOR (MBM) OUTPUT OPERATION

PCM4222

SBAS399A – OCTOBER 2006 – REVISED MARCH 2007

Table 9. DSD Output Rate Selection

DSDMODE (pin 24)

DSD OUTPUT RATE

LO

64x Oversampled Data

HI

128x Oversampled Data

When driving capacitive loads greater than 30pF with the DSD data and clock outputs, it is recommended that

external buffers be utilized to ensure data and clock integrity at the receiving device(s).

Details regarding dynamic performance for the DSD output are shown in the Electrical Characteristics table of

this datasheet. Figure 3 and the Electrical Characteristics: Audio Interface Timing table detail the timing

parameters for the DSD output.

Figure 46. Simplified Block Diagram for DSD Mode Operation

The PCM4222 supports direct data output from the multi-bit delta sigma modulators. This mode allows the use

of external, user-defined digital filtering and/or processing. Figure 47 illustrates the functional concept for the

multi-bit modulator (or MBM) output mode, as well as the output data format.

The MBM output mode is enabled or disabled using the MODEN input (pin 23). Table 10 summarizes the

operation of the MODEN pin. When MBM mode is enabled, both the PCM and DSD output modes are disabled,

and multiple pins are re-mapped. Table 11 summarizes the pin mapping for MBM mode, compared to the PCM

and DSD output modes. The PCMEN input (pin 16) must be forced high when the multi-bit output is enabled;

forcing this input high enables both the left and right channel multi-bit output data.

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