1997 Apr 01

14

Philips Semiconductors

Preliminary specification

1K dual mode serial EEPROM

PCB2421

10 AC CHARACTERISTICS

Notes

1. The rise time for SDA returning HIGH must be observed after this period.

2. This is the time that the bus must be free before a new transmission can start.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DDC1 mode (transmit-only; unidirectional)

output valid from VCLK

see Fig.12; note 1

−

1

−µs

VCLK HIGH time

see Fig.12

20

−−µs

VCLK LOW time

see Fig.12

20

−−µs

mode transition time

see Fig.3; note 1

−

500

−

ns

input filter spike suppression time

−−

100

ns

DDC1 mode power-up time

see Fig.4

−

5

−µs

serial clock frequency

0

−

100

kHz

serial clock HIGH time

4

−−µs

serial clock LOW time

4.7

−−µs

SCL and SDA rise time

−−

1

µs

SCL and SDA fall time

−−

0.3

µs

START condition hold time

4

−−µs

START condition set-up time

4.7

−−µs

data input hold time

0

−−µs

data input set-up time

250

−−

ns

STOP condition set-up time

4

−−µs

bus free time

note 2

4.7

−−µs

input filter spike suppression

−−

100

ns