1997 Mar 03

6

Philips Semiconductors

Objective specification

Stand-alone OSD for monitor applications

PCB8517

The PCB8517 provides the following 3 types of

transmission sequence:

• Sequence A: R ⇒ CA ⇒ D ⇒ R ⇒ CA ⇒ D etc.

• Sequence B: R ⇒ CA ⇒ D ⇒ CA ⇒ D ⇒ CA ⇒ D etc.

• Sequence C: R ⇒ CB ⇒ D ⇒ D ⇒ D ⇒ D etc.

Where: R = row address,

CA = column address A, CB = column address B,

D = data of RAM.

The column address will be increased by 1 automatically

after each bit of data has been stored into the RAM.

In sequence C, if the column address of the last data is

1FH, the row address will also be increased by 1.

The sequence A is particularly suitable for updating small

amounts of data between different rows. However, if the

current information byte has the same row address as the

previous one, sequence B is recommended. For a greater

information update, such as a power-up situation,

sequence C should be used.

Bit B7 in Table 2 is used to distinguish between row or

column address and bit B6 is used to distinguish between

column address A or B. When A or B sequence is

transmitted, the column address should be formatted as

column address A, and the data format of column

address B is used for sequence C. There are some

limitations on using mixed formats during a single

transmission, for example when pin EN has been pulled to

LOW once.

Allowed:

• From A to B or C

• From B to A.

Not allowed:

• From C to A or B.

Table 2

Data format

Note

1. X = don’t care.

Internal RAM organization (see Fig.4)

The internal RAM is addressed with rows 0 to 10 and columns 0 to 31. The OSD character display buffers are located in

columns 0 to 23 of rows 0 to 9. Each display buffer contains a character ROM address and the colour control bit

corresponding to a display location on the monitor screen.

Each row data is associated with two control registers which are located at columns 30 and 31 of their respective row.

Also three window control registers for three windows together with three frame control register occupy the first

13 columns of row 10.

ADDRESS

B7

B6

B5

B4

B3

B2

B1

B0

Row address

1

X

X

X

R3

R2

R1

R0

Column address A

0

0

X

C4

C3

C2

C1

C0

Column address B

0

1

X

C4

C3

C2

C1

C0