PCD5002USLASH10 datasheet(7/48 Pages) PHILIPS

7 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

Address codewords are identified by an MSB at logic 0

and are coded as shown in Fig.3. A user address or RIC

consists of 21 bits. Only the upper 18 bits are encoded in

the address codeword (bits 2 to 19). The lower 3 bits

designate the frame number (0 to 7) in which the address

is transmitted.

Four different call types (‘numeric’, ‘alphanumeric’ and two

‘alert only’ types) can be distinguished. The call type is

determined by two function bits in the address codeword

(bits 20 and 21), as shown in Table 1.

Alert-only calls consist only of a single address codeword.

Numeric and alphanumeric calls have message

codewords following the address. A message causes the

frame structure to be temporarily suspended. Message

codewords are sent until the message is completed, with

only the sync words being transmitted in their expected

positions.

Message codewords are identified by an MSB at logic 1

and are coded as shown in Fig.3. The message

information is stored in a 20-bit field (bits 2 to 21).

The standard data format is determined by the call type: 4

bits per digit for numeric messages and 7 bits per (ASCII)

character for alphanumeric messages.

Each codeword is protected against transmission errors by

10 CRC check bits (bits 22 to 31) and an even-parity bit

(bit 32). This permits correction of a maximum of 2 random

errors or up to 3 errors in a burst of 4 bits (a 4-bit burst

error) per codeword.

8.3

The APOC-1 paging code

The APOC-1 paging code is fully POCSAG compatible

and involves the introduction of batch grouping and a

Batch Zero Identifier. This reserved address codeword

indicates the start of a ‘cycle’ of 5 or 15 batches long and

is transmitted immediately after a sync word.

Cycle transmission must be coherent i.e. a transmission

starting an integer number of cycle periods after the start

of the previous one.

Broadcast message data may be included in a

transmission. This information may occupy any number of

message codewords and immediately follows the batch

zero identifier of the first cycle after preamble.

The presence of data is indicated by the function bits in the

batch zero identifier: 1,1 indicates ‘no broadcast data’.

Any other combination indicates a broadcast message.

The PCD5002 can be configured for POCSAG or APOC-1

operation via SPF programming. The batch zero identifier

is programmable and can be stored in any identifier

location in EEPROM.

Fig.3 POCSAG code structure.

handbook, full pagewidth

PREAMBLE

BATCH 1

BATCH 2

BATCH 3

LAST BATCH

SYNC | CW CW | CW CW | . . . . . | CW CW

FRAME 0

FRAME 1

FRAME 7

10101 . . . 10101010

Address code-word

Message code-word

18-bit address

2 function bits

10 CRC bits

20-bit message

10 CRC bits

MCD456

PCD5002U/10 Datasheet(PDF) 7 Page - NXP Semiconductors

PCD5002U/10 Datasheet(HTML) 7 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL