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ST92F124 Datasheet(PDF) 372 Page - STMicroelectronics |
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ST92F124 Datasheet(HTML) 372 Page - STMicroelectronics |
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372 / 429 page ![]() 372/429 10-BIT ANALOG TO DIGITAL CONVERTER (ADC) REGISTER DESCRIPTION (Cont’d) CONTROL LOGIC REGISTER 1 (CLR1) R252 - Read/Write Register Page: 63 Reset Value: 0000 1111 (0Fh) Bits 7:4 = SC[3:0]: Start Conversion Channel These four bits define the starting analog input channel (Autoscan Mode). The first channel ad- dressed by SC[3:0] is converted, then the channel number is incremented for the successive conver- sion, until channel 15 (1111) is converted. When SC3, SC2, SC1 and SC0 are all set, only channel 15 will be converted. Bits 3:0 = CC[3:0]: Compare Channels The programmed value corresponds to the first of the two adjacent channels (A) on which it is possi- ble to define a level window for the converted ana- log input (see Table 68). Note: If a write access to this register occurs, the conversion is re-started from the SC[3:0] channel. CONTROL LOGIC REGISTER 2 (CLR2) R253 - Read/Write Register Page: 63 Reset Value: 1010 0000 (A0h) Bits 7:5 = PR[2:0]: INTCLK Frequency Prescaler These bits determine the ratio between the ADC clock and the system clock (INTCLK) according to Table 69. 70 SC3 SC2 SC1 SC0 CC3 CC2 CC1 CC0 Table 68. Compare Channels definition CC[3:0] Channel A Channel B 0000 15 0 0001 0 1 0010 1 2 0011 2 3 0100 3 4 0101 4 5 0110 5 6 0111 6 7 1000 7 8 1001 8 9 1010 9 10 1011 10 11 1100 11 12 1101 12 13 1110 13 14 1111 14 15 70 PR2 PR1 PR0 EXTG INTG POW CONT ST Table 68. Compare Channels definition CC[3:0] Channel A Channel B Table 69. Prescaler programming PR[2:0] TA/D clock/ TINTCLK fADC (MHz) TSample (µs) TConv (µs) fADC (MHz) TSample (µs) TConv (µs) fADC (MHz) TSample (µs) TConv (µs) @TINTCLK= 8MHz @TINTCLK= 20MHz @TINTCLK=24MHz 000 2 4.00 2 7 10.00 Not Allowed 12.00 Not Allowed 001 4 2.00 4 14 5.00 Not Allowed 6.00 Not Allowed 010 6 1.33 6 21 3.33 2.4 8.4 4.00 2 7 011 8 1.00 8 28 2.50 3.2 11.2 3.00 2.66 9.33 100 10 0.80 Not Allowed 2.00 4 14 2.40 3.33 11.66 101 12 0.66 Not Allowed 1.66 4.8 16.8 2.00 4 14 110 14 0.57 Not Allowed 1.43 5.6 19.6 1.71 4.66 16.33 111 16 0.50 Not Allowed 1.25 6.4 22.4 1.50 5.33 18.66 9 |
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