PCF5077T datasheet(4/24 Pages) PHILIPS

4 / 24 page

1997 Nov 19

Philips Semiconductors

Preliminary speciﬁcation

Power ampliﬁer controller for GSM and

PCN systems

PCF5077T

PINNING

SYMBOL

DESCRIPTION

sensor signal input

programmable 3-state output

VDDA1

analog supply voltage 1

BVS

buffered sensor signal output

TRIG

trigger signal input

VDDD

digital supply voltage

power-down input (active LOW)

CLK13

13 MHz master clock input

(low-swing)

STROBE

serial bus strobe signal input

CLK

serial bus clock signal input

DATA

serial bus data signal input

VSSD

digital ground

VSSA

analog ground

VINT(O)

integrator output

VINT(N)

integrator inverting input

VDDA2

analog supply voltage 2 (for OP4)

Fig.2 Pin configuration.

handbook, halfpage

PCF5077T

MGK909

VDDA1

BVS

TRIG

VDDD

CLK13

STROBE

CLK

DATA

VSSD

VSSA

VINT(O)

VINT(N)

VDDA2

FUNCTIONAL DESCRIPTION

General

This CMOS device integrates operational amplifiers, two

digital-to-analog converters and a serial bus interface to

implement an ‘Integrating-Controller’ (see Fig.1). It is

designed to control both the power level and the up- and

down-ramping of GSM/PCN transmit bursts.

The GSM/PCN power-up and power-down ramping curves

are generated on-chip, using an internal clock frequency of

2.166 MHz

, that is generated internally by

dividing the external 13 MHz clock signal by six.

Generally, the power amplifier is ramped-up after a rising

edge on pin TRIG and ramped-down after a falling edge.

The content of the power level register (bits PL7 to PL0)

determines which of the 2

× 256 possible values the top of

the burst will have.

To match the controller to different power modules and

sensors several parameters must be adapted.

The following parameters influence the performance of the

transmission system:

• The external capacitor C1 in Fig.1 determines the

maximum bandwidth of the power control loop,

clk

-------





depending on the highest steepness of the control curve

of the power module and on the sensor attenuation.

• The maximum output voltage at pin VINT(O) to protect the

power module: the limiting value of VINT(O) can be set to

4, 3.3 or 2.55 V, depending on the contents of the limiter

ringing at VINT(O) (typ. 200 mV peak-to-peak value) but it

will not be transferred to the antenna because the power

module is in saturation. The limiter register bits Lim1

and Lim0 can be used to switch off the limiter option

(see Table 5).

• The home position at V

INT(O): the integrator output

voltage at home position (PD = HIGH and TRIG = LOW)

is programmed by means of the VHOME register.

Bits Vh5 to Vh0 are fed into a 6-bit DAC that generates

a part of VHOME.

• The temperature behaviour of the home position:

bits DVh1 and DVh0 can be used to compensate

temperature dependencies (

−2or −4 mV/K) of the

control curves of the power module. This completes the

setting of VHOME.

• The KICK voltage: the 6 bits of the VKICK register

(Vk5 to Vk0) determine the differential integrator input

voltage just after a ramp-up starting signal is detected.

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