PCF8578USLASH2 datasheet(14/44 Pages) PHILIPS

14 / 44 page

1998 Sep 08

Philips Semiconductors

Product speciﬁcation

LCD row/column driver for dot matrix

graphic displays

PCF8578

7.5

Internal clock

The clock signal for the system may be generated by the

internal oscillator and prescaler. The frequency is

determined by the value of the resistor ROSC, see Fig.9.

For normal use a value of 330 k

Ω is recommended.

The clock signal, for cascaded PCF8579s, is output at CLK

and has a frequency 1

⁄6 (multiplex rate 1 : 8, 1 : 16 and

1 : 32) or 1

⁄8 (multiplex rate 1 : 24) of the oscillator

frequency.

Fig.9

Oscillator frequency as a function of

external oscillator resistor, ROSC.

To avoid capacitive coupling, which could adversely affect oscillator

stability, ROSC should be placed as closely as possible to the OSC

pin. If this proves to be a problem, a filtering capacitor may be

connected in parallel to ROSC.

MSA837

102

103

104

10 3

10 2

f OSC

(kHz)

R(k

Ω )

OSC

7.6

External clock

If an external clock is used, OSC must be connected to

VDD and the external clock signal to CLK. Table 4

summarizes the nominal CLK and SYNC frequencies.

7.7

Timing generator

The timing generator of the PCF8578 organizes the

internal data flow of the device and generates the LCD

frame synchronization pulse SYNC, whose period is an

integer multiple of the clock period. In cascaded

applications, this signal maintains the correct timing

relationship between the PCF8578 and PCF8579s in the

system.

7.8

Row/column drivers

Outputs R0 to R7 and C32 to C39 are fixed as row and

column drivers respectively. The remaining 24 outputs

R8/C8 to R31/C31 are programmable and may be

configured (in blocks of 8) to be either row or column

drivers. The row select signal is produced sequentially at

each output from R0 up to the number defined by the

multiplex rate (see Table 1). In mixed mode the remaining

outputs are configured as columns. In row mode all

programmable outputs (R8/C8 to R31/C31) are defined as

row drivers and the outputs C32 to C39 should be left

open-circuit.

Using a 1 : 16 multiplex rate, two sets of row outputs are

driven, thus facilitating split-screen configurations, i.e. a

row select pulse appears simultaneously at R0 and

R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex

rate of 1 : 8, four sets of row outputs are driven

simultaneously. Driver outputs must be connected directly

to the LCD. Unused outputs should be left open-circuit.

In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are

rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32

R0 to R31/C31 are rows.

Table 4

Signal frequencies required for nominal 64 Hz frame frequency; note 1.

Notes

1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state.

2. ROSC = 330 kΩ.

OSCILLATOR

FREQUENCY

fOSC(2) (Hz)

FRAME FREQUENCY

fSYNC (Hz)

MULTIPLEX RATE (n)

DIVISION

RATIO

CLOCK FREQUENCY

fCLK (Hz)

12288

1 : 8, 1 : 16, 1 : 32

2048

12288

1 : 24

1536

PCF8578U/2 Datasheet(PDF) 14 Page - NXP Semiconductors

PCF8578U/2 Datasheet(HTML) 14 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL