PCK2023DL datasheet(3/30 Pages) PHILIPS

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Philips Semiconductors

Product data

PCK2023

CK408 (66/100/133/200 MHz) spread

spectrum differential system clock generator

2001 Sep 07

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

ref

3.3 V 14.318 MHz clock output.

XTAL_In

14.318 MHz crystal input.

XTAL_Out

14.318 MHz crystal output.

44, 45, 48, 49, 51, 52

CPU & CPU

[2:0]

Differential CPU clock outputs.

3V66_0

3.3 V 66 MHz clock output.

3V66_1/VCH

3.3 V selectable through I2C to be 66 MHz or 48 MHz

66In/3V66_5

66 MHz input to buffered 66Buff and PCI or 66 MHz clock from internal VCO.

21, 22, 23

66Buff [2:0] / 3V66 [4:2]

66 MHz buffered outputs from 66 input or 66 MHz clocks from internal VCO.

5, 6, 7

PCIF

[2:0]

33 MHz clocks divided down from 66 input or divided down from 3V66.

10, 11, 12, 13, 16, 17,

PCI

[6:0]

PCI clock outputs divided down from 66 input or divided down from 3V66.

USB

Fixed 48 MHz clock output.

DOT

Fixed 48 MHz clock output.

Special 3.3 V 3 level input for mode selection.

54, 55

S1, S0

3.3 V LVTTL inputs for CPU frequency selection.

Iref

A precision resistor is attached to this pin which is connected to the internal current

reference.

Mult0

3.3 V LVTTL input for selecting the current multiplier for the CPU outputs.

PWRDWN

3.3 V LVTTL input for PowerDown active low.

PCI_Stop

3.3 V LVTTL input for PCI_Stop active low.

CPU_Stop

3.3 V LVTTL input for CPU_Stop active low.

Vtt_Pwrgd

3.3 V LVTTL input is a level sensitive strobe used to determine when S [2:0] and Mult0

inputs are valid and ok to be sampled (active low).

SDATA

I2C compatible SDATA.

SCLOCK

I2C compatible SCLOCK.

1, 8, 14, 19, 32, 37, 46,

VDD

3.3 V power supply for outputs.

VDDA

3.3 V power supply for PLL.

4, 9, 15, 20, 31, 36, 41,

VSS

Ground for outputs.

VSSA

Ground for PLL.

PCK2023DL Datasheet(PDF) 3 Page - NXP Semiconductors

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