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SLRC61002HNT Datasheet(PDF) 22 Page - NXP Semiconductors |
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SLRC61002HNT Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 139 page  NXP Semiconductors SLRC610 High-performance ICODE frontend SLRC610 and SLRC610 plus 001aam303 MSB acknowledgement signal from slave acknowledgement signal from receiver clock line held low while interrupts are serviced byte complete, interrupt within slave 1 2 7 8 9 1 2 9 ACK ACK 3 - 8 Sr or P P Sr S or Sr Figure 14. Data transfer on the I2C- bus 8.4.4.6 I2C 7-bit addressing During the I2C-bus addressing procedure, the first byte after the START condition is used to determine which slave will be selected by the master. Alternatively the I2C address can be configured in the EEPROM. Several address numbers are reserved for this purpose. During device configuration, the designer has to ensure, that no collision with these reserved addresses in the system is possible. Check the corresponding I2C specification for a complete list of reserved addresses. For all SLRC610 devices the upper 5 bits of the device bus address are reserved by NXP and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slave address can be freely configured by the customer in order to prevent collisions with other I2C devices by using the interface pins (refer to Table 8) or the value of the I2C address EEPROM register (refer to Table 30). 001aam304 Bit 6 Bit 5 Bit 4 slave address Bit 3 Bit 2 Bit 1 Bit 0 R/W MSB LSB Figure 15. First byte following the START procedure 8.4.4.7 I2C-register write access To write data from the host controller via I2C to a specific register of the SLRC610 the following frame format shall be used. The read/write bit shall be set to logic 0. The first byte of a frame indicates the device address according to the I2C rules. The second byte indicates the register address followed by up to n-data bytes. In case the address indicates the FIFO, in one frame all n-data bytes are written to the FIFO register address. This enables for example a fast FIFO access. 8.4.4.8 I2C-register read access To read out data from a specific register address of the SLRC610 the host controller shall use the procedure: First a write access to the specific register address has to be performed as indicated in the following frame: The first byte of a frame indicates the device address according to the I2C rules. The second byte indicates the register address. No data bytes are added. The read/write bit shall be logic 0. SLRC610 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5.1 — 3 January 2024 22 / 139 |
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