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MPC8313ECVRAFF Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc

Part # MPC8313ECVRAFF
Description  PowerQUICC??II Pro Processor Hardware Specifications
PDF  88 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8313ECVRAFF Datasheet(HTML) 45 Page - Freescale Semiconductor, Inc

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
45
I
2C
12 I2C
This section describes the DC and AC electrical characteristics for the I2C interface.
12.1
I2C DC Electrical Characteristics
Table 42 provides the DC electrical characteristics for the I2C interface.
12.2
I2C AC Electrical Specifications
Table 43 provides the AC timing parameters for the I2C interface.
Table 42. I2C DC Electrical Characteristics
At recommended operating conditions with NVDD of 3.3 V ± 10%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7
× NVDD
NVDD + 0.3
V
Input low voltage level
VIL
–0.3
0.3
× NVDD
V
Low level output voltage
VOL
00.2
× NVDD
V1
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV 20 + 0.1 × CB
250
ns
2
Pulse width of spikes which must be suppressed by the input
filter
tI2KHKL
050
ns
3
Capacitance for each I/O pin
CI
—10
pF
Input current
(0 V
≤VIN ≤ NVDD)
IIN
—± 5
μA4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the
MPC8313E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter
used.
4. I/O pins will obstruct the SDA and SCL lines if NVDD is switched off.
Table 43. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 42).
Parameter
Symbol 1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
1.3
—
μs
High period of the SCL clock
tI2CH
0.6
—
μs
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
tI2SXKL
0.6
—
μs
Data setup time
tI2DVKH
100
—
ns



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