ADATE207

Rev. 0 | Page 32 of 36

Position

Description

Reset State

0x0 selects Channel 0 comparator high.

0x1 selects Channel 0 comparator low.

0x2 selects Channel 1 comparator high.

0x3 selects Channel 1 comparator low.

0x4 selects Channel 2 comparator high.

0x5 selects Channel 2 comparator low.

0x6 selects Channel 3 comparator high.

0x7 selects Channel 3 comparator low.

Bit 03

TMU Arm Enable. A zero tristates the TMU Stop output.

0

Bits[02:00]

TMU Arm Channel Select Multiplexer. A binary encoded data field.

0x00

0x0 selects Channel 0 comparator high.

0x1 selects Channel 0 comparator low.

0x2 selects Channel 1 comparator high.

0x3 selects Channel 1 comparator low.

0x4 selects Channel 2 comparator high.

0x5 selects Channel 2 comparator low.

0x6 selects Channel 3 comparator high.

0x7 selects Channel 3 comparator low.

Name:

Channel Multiplex Enable

Address:

0x1D

Type:

Read/Write

Table 37. Channel Multiplex Enable

Position

Description

Reset State

Bits[15:02]

Not Used.

0x0000

Bit 01

CH2 Multiplex Enable. This channel can be 2-way multiplexed. Setting this bit to 1 enables Channel 3

to be multiplexed on Channel 2.

0

Bit 00

CH0 Multiplex Enable. This channel can be 2-way multiplexed. Setting this bit to 1 enables Channel 1

to be multiplexed on Channel 0.

0

Name:

Channel Status

Address:

0x1E

Type:

Read

Table 38. Channel Status

Position

Description

Reset State

Bit 15

Channel 3 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the

accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the

AFRs or fail counter for Channel 3.

0x0

Bit 14

Channel 2 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the

accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the

AFRs or fail counter for Channel 2.

0x0

Bit 13

Channel 1 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the

accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the

AFRs or fail counter for Channel 1.

0x0

Bit 12

Channel 0 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the

accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the

AFRs or fail counter for Channel 0.

0x0

Bit 11

Channel 3 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of

the timing error flags of the channel. More details of the error can be found by reading the error flags

for Channel 3.

0x0