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56F8014 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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56F8014 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 125 page ![]() 56F8014 Features 56F8014 Technical Data, Rev. 9 Freescale Semiconductor 7 Preliminary — Taking into account values setting ADC high- and low-limit registers, each complementary PWM signal pair allows selection of a PWM supply source from: – PWM generator – External GPIO – Internal timers – ADC conversion result • Two independent 12-bit Analog-to-Digital Converters (ADCs) — 2 x 4 channel inputs — Supports both simultaneous and sequential conversions — ADC conversions can be synchronized by both PWM and timer modules — Sampling rate up to 2.67MSPS — 8-word result buffer registers — ADC Smart Power Management (Auto-standby, auto-powerdown) • One 16-bit multi-purpose Quad Timer module (TMR) — Up to 96MHz operating clock — Four independent 16-bit counter/timers with cascading capability — Each timer has capture and compare capability — Up to 12 operating modes • One 16-bit multi-purpose Quad Timer module (TMR) — Up to 96MHz operating clock — Four independent 16-bit counter/timers with cascading capability — Each timer has capture and compare capability — Up to 12 operating modes • One 16-bit multi-purpose Quad Timer module (TMR) — Up to 96MHz operating clock — Four independent 16-bit counter/timers with cascading capability — Each timer has capture and compare capability — Up to 12 operating modes • Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources • Up to 26 General-Purpose I/O (GPIO) pins with 5V tolerance • Integrated Power-On Reset and Low-Voltage Interrupt Module • Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals • Clock Sources: — On-chip relaxation oscillator — External clock source • On-chip regulators for digital and analog circuitry to lower cost and reduce noise • JTAG/EOnCE debug programming interface for real-time debugging |
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