AD9995KCPRL datasheet(32/60 Pages) AD

32 / 60 page

AD9995

–32–

AD9995

–33–

A/D Converter

The AD9995 uses a high performance ADC architecture

optimized for high speed and low power. Differential nonlinearity

(DNL) performance is typically better than 0.5 LSB.The ADC

uses a 2 V input range. See TPC 2 and TPC 3 for typical linearity

and noise performance plots for the AD9995.

Optical Black Clamp

The optical black clamp loop is used to remove residual offsets

in the signal chain and to track low frequency variations in the

CCD’s black level. During the optical black (shielded) pixel inter-

val on each line, the ADC output is compared with a fixed black

level reference, selected by the user in the Clamp Level register.

The value can be programmed between 0 LSB and 255 LSB in

256 steps. The resulting error signal is filtered to reduce noise,

and the correction value is applied to the ADC input through a

D/A converter. Normally, the optical black clamp loop is turned

on once per horizontal line, but this loop can be updated more

slowly to suit a particular application. If external digital clamp-

ing is used during the postprocessing, the AD9995 optical black

clamping may be disabled using Bit D2 in the OPRMODE regis-

ter.When the loop is disabled, the Clamp Level register may still

be used to provide programmable offset adjustment.

The CLPOB pulse should be placed during the CCD’s optical

black pixels. It is recommended that the CLPOB pulse dura-

tion be at least 20 pixels wide to minimize clamp noise. Shorter

pulsewidths may be used, but clamp noise may increase, and the

ability to track low frequency variations in the black level will

be reduced. See the Horizontal Clamping and Blanking section

and the Horizontal Timing Sequence Example section for timing

examples.

Digital Data Outputs

The AD9995 digital output data is latched using the DOUT

PHASE register value, as shown in Figure 33. Output data timing

is shown in Figure 8a. It is also possible to leave the output latches

transparent so that the data outputs are valid immediately from

the A/D converter. Programming the AFE CONTROL register bit

D4 to 1 will set the output latches transparent. The data outputs

can also be disabled (three-stated) by setting the AFE CONTROL

The data output coding is normally straight binary, but the

coding my be changed to gray coding by setting the AFE CON-

TROL register Bit D5 to 1.

REV. 0

AD9995KCPRL Datasheet(PDF) 32 Page - Analog Devices

AD9995KCPRL Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL