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PLHS501IA Datasheet(PDF) 9 Page - NXP Semiconductors

Part # PLHS501IA
Description  Programmable macro logic PML
PDF  12 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PLHS501IA Datasheet(HTML) 9 Page - NXP Semiconductors

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Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501I
Programmable macro logic
PML
™
October 22, 1993
9
MACRO CELL SPECIFICATIONS1 (SNAP Resource Summary Designations in Parantheses)
Commercial:Tamb = 0°C to +75°C, 4.75V ≤ VCC ≤ 5.25V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω
Industrial:
Tamb = –40°C to +85°C, 4.5V ≤ VCC ≤ 5.5V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω
Input Buffer
(DIN501 [Non-inverting], NIN501 [Inverting])
I
X
Y
LIMITS
SYMBOL
MIN
TYP
MAX
UNIT
∆t
HL
0.05
0.1
0.15
ns/p-term
∆t
LH
–0.02
–0.05
–0.08
ns/p-term
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
NOTES
tPHL
tPLH
X
X
I
I
4.5
5
5.5
6
6.5
7.5
ns
ns
With 0 p-terms load
tPHL
tPLH
Y
Y
I
I
2.5
4
3
4
3.5
4.5
ns
ns
With 0 p-terms load
Input Pins: 1 – 7, 9 – 14, 41 – 45, 48 – 52.
Bidirectional Pins: 15 – 18, 37 – 40.
Maximum internal fan-out: 16 p-terms on X or Y.
NAND Output Buffer with 3-State Control
(TOU501)
Tri–Ctrl
In
Out
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
tPHL
tPLH
Out
Out
In
In
8.5
8.5
14.0
14.0
17.5
16
ns
ns
tOE2
tOD2
Out
Out
Tri-Ctrl
Tri-Ctrl
8.5
8.5
15
12.5
18.5
17.0
ns
ns
Output Pins: 24 – 27.
Internal Foldback NAND
(FBNAND)
Output
Input
LIMITS
SYMBOL
MIN
TYP
MAX
UNIT
∆t
PHL
0.05
0.1
0.15
ns/p-term
∆t
PLH
–0.0
–0.05
–0.1
ns/p-term
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
NOTES
tPHL
tPLH
Out
Any
4.0
5.5
4.5
6.5
6.8
8
ns
ns
With 0 p-terms load
Maximum internal loading of 16 terms.
Notes are on following page.



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