6.3.8 Input ESD Protection

The OPAx310-Q1 family incorporates internal ESD protection circuits on all pins. For inputs, this protection

primarily consists of fail safe ESD input structures which feature no current-steering diodes connected between

the input and positive power-supply pin as shown in the Figure 6-5. This feature is very useful during power

sequencing scenarios where input signal can be present before the positive power supply rail. A fail safe input

ESD structure prevents any short between inputs and positive power supply.

6.3.9 Shutdown Function

The OPAx310-Q1 S devices feature SHDN pins that disable the op amp, placing the op amp into a low-power

standby mode. In this mode, the op amp typically consumes less than 500-nA at room temperature. The SHDN

pins are active low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low.

The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown

feature lies around 500-mV (typical) and does not change with respect to the supply voltage. Hysteresis has

been included in the switching threshold to provide for smooth switching characteristics. To make sure of optimal

shutdown behavior, the SHDN pins must be driven with valid logic signals. A valid logic low is defined as a

voltage between V– and (V–) + 0.2V. A valid logic high is defined as a voltage between (V–) + 1.2V and V+. To

enable the amplifier, the SHDN pins must be driven to a valid logic high. To disable the amplifier, the SHDN pins

must be driven to a valid logic low. TI highly recommends that the shutdown pin be connected to a valid high or

a low voltage or driven. The maximum voltage allowed at the SHDN pins is (V+) + 0.5V. Exceeding this voltage

level damages the device.

The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and

quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature

can be used to greatly reduce the average current and extend battery life. The enable and disable time is

targeted to be under 1µs for full shutdown of all channels. When disabled, the output assumes a high-impedance

state. This architecture allows the OPAx310S-Q1 to be operated as a gated amplifier (or to have the device

output multiplexed onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and

increases as load resistance increases. To make sure that shutdown (disable) is within a specific shutdown time,

the specified 10-kΩ load to midsupply (VS / 2) is required.

6.4 Device Functional Modes

The OPAx310-Q1 devices have one functional mode. These devices are powered on as long as the power-

supply voltage is between 1.5V (±0.75V) and 5.5V (±2.75V).

The OPAx310-Q1S devices feature a shutdown pin, which can be used to place the op amp into a low-power

mode. See Shutdown Function for more information.

OPA310-Q1

SBOSAI0A – DECEMBER 2023 – REVISED MAY 2024

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