56F8023_07 datasheet(6/156 Pages) FREESCALE

6 / 156 page

56F8023 Data Sheet, Rev. 3

Freescale Semiconductor

Preliminary

–External GPIO

– Internal timers

– Analog comparator outputs

– ADC conversion result which compares with values of ADC high- and low-limit registers to set

PWM output

•

Two independent 12-bit Analog-to-Digital Converters (ADCs)

— 2 x 3 channel inputs

— Supports both simultaneous and sequential conversions

— ADC conversions can be synchronized by both PWM and timer modules

— Sampling rate up to 2.67MSPS

— 16-word result buffer registers

•

Two internal 12-bit Digital-to-Analog Converters (DACs)

—2

μs settling time when output swing from rail to rail

— Automatic waveform generation generates square, triangle and sawtooth waveforms with

programmable period, update rate, and range

•

One 16-bit multi-purpose Quad Timer module (TMR)

— Up to 96MHz operating clock

— Eight independent 16-bit counter/timers with cascading capability

— Each timer has capture and compare capability

— Up to 12 operating modes

•

One Queued Serial Communication Interface (QSCI) with LIN Slave functionality

— Full-duplex or single-wire operation

— Two receiver wake-up methods:

– Idle line

– Address mark

— Four-bytes-deep FIFOs are available on both transmitter and receiver

•

One Queued Serial Peripheral Interfaces (QSPI)

— Full-duplex operation

— Master and slave modes

— Four-words-deep FIFOs available on both transmitter and receiver

— Programmable Length Transactions (2 to 16 bits)

•

One Inter-Integrated Circuit (I2C) port

— Operates up to 400kbps

— Supports both master and slave operation

— Supports both 10-bit address mode and broadcasting mode

•

One 16-bit Programmable Interval Timer (PIT)

•

Two analog Comparators (CMPs)

56F8023 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc

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