Analog Integrated Circuit Device Data

Freescale Semiconductor

7

33970

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT AND CLOCK TIMINGS

SIN, COS Output Turn ON Delay Time (Time from Rising CS Enabling

Outputs to Steady State Coil Voltages and Currents) (14)

–

–

1.0

ms

SIN, COS Output Turn OFF Delay Time (Time from Rising CS Disables

Outputs to Steady State Coil Voltages and Currents) (14)

–

–

1.0

ms

Uncalibrated Oscillator Cycle Time

0.65

1.0

1.7

µs

Calibrated Oscillator Cycle Time

Cal Pulse = 8.0

µs, PECCR D4 = Logic [0]

Cal pulse = 8.0

µs, PECCR D4 = Logic [1]

1.0

0.9

1.1

1.0

1.2

1.1

µs

Maximum Pointer Speed (15)

–

–

400

°/s

Maximum Pointer Acceleration (15)

–

–

4500

SPI INTERFACE TIMING (16)

Recommended Frequency of SPI Operation

–

1.0

3.0

MHz

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (17)

–

50

167

ns

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (17)

–

50

167

ns

SI to Falling Edge of SCLK (Required Setup Time) (17)

–

25

83

ns

Required High State Duration of SCLK (Required Setup Time) (17)

–

–

167

ns

Required Low State Duration of SCLK (Required Setup Time) (17)

–

–

167

ns

Falling Edge of SCLK to SI (Required Hold Time) (17)

–

25

83

ns

SO Rise Time

–

25

50

ns

SO Fall Time

–

25

50

ns

SI, CS, SCLK, Incoming Signal Rise Time (18)

–

–

50

ns

SI, CS, SCLK, Incoming Signal Fall Time (18)

–

–

50

ns

Falling Edge of RST to Rising Edge of RST (Required Setup Time) (17)

–

–

3.0

µs

Rising Edge of CS to Falling Edge of CS (Required Setup Time) (17), (19)

–

–

5.0

µs

Rising Edge of RST to Falling Edge of CS (Required Setup Time) (17)

–

–

5.0

µs

Notes

14.

Maximum specified time for the 33970 is the minimum guaranteed time needed from the microcontroller.

15.

The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally

calibrated clock frequency of 1.0 MHz. These are not 100 percent tested.

16.

The device shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the temperature

range specified. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device shall

be fully functional for slower clock speeds. See Figure 4 and 5.

17.

The maximum setup time specified for the 33970 is the minimum time needed from the microcontroller to guarantee correct operation.

18.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

19.

The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes