XRT84L38 datasheet(73/453 Pages) EXAR

73 / 453 page

XRT84L38

REV. 1.0.1

OCTAL T1/E1/J1 FRAMER

DMA-0 WRITE DMA INTERFACE

DMA 0 Controller Interface handles data transfer between external memory and the selected Transmit HDLC

Buffer.

The DMA cycle starts when the XRT84L38 asserts the REQ0 output pin. The external DMA Controller then

responds by asserting the ACK0 input pin. The contents of the Microprocessor Interface bi-directional data bus

are latched into the XRT84L38 each time the pWRL (Write Strobe) input pin is strobed “Low”.

The XRT84L38 ends the DMA cycle by negating the DMA request input (REQ0) while WR is still active. The

external DMA Controller acknowledges the end of DMA Transfer by driving the ACK0 input pin “High”.

1.5

Memory and Register Map

This section presents a complete list of the Framer external memory address map and the internal memory

map. In addition, the allocations of the three internal storage spaces is depicted.

1.5.1

Memory Mapped I/O Indirect Addressing

The XRT84L38 employs a complete indirect addressing approach for the Microprocessor Interface; in order to

support multiple channel implementations, maintaining rich user-controlled features, minimizing the total pin

count and providing future scalability without sacrificing performance for microcontroller access. Eight address

bits are used with the 4 MSB (most significant bits) identifying each of the eight framers channels and the 4

LSBs to address the indirect mapping registers.

The XRT84L38 framer has approximately 5,800 addressable spaces internally. If each of these addresses has

to be accessed directly, it would require a 13-bit address bus. In order to control total pin count as well as to

provide future scalability, the XRT84L38 employs an Indirect Addressing Scheme. Using this technique, only 7

address input pins on the XRT84L38 are needed.

The addressable spaces within the XRT84L38 are divided into groups of registers. Each register group

consists of a specific number of indirect address registers and a same number of indirect data registers with

the exception of LAPD Buffer 0 and 1. Of the 7 total address input bits, the 3 MSB pins are used to identify

each of eight T1/E1 framer channels. The remaining 4 LSB bits are used to address the register groups.

Table 8

indicates the address mapping of all the register groups within the XRT84L38. Please note that the

indirect address registers are with even addresses and the corresponding indirect data registers are with odd

addresses with the exception of, again, the LAPD Buffer 0 and 1. The n corresponds to the channel number.

FIGURE 16. DMA MODE FOR THE XRT84L38 AND A MICROPROCESSOR

REQ[1:0]

ACK[1:0]

μPCLK

DATA[7:0]

Microprocessor

XRT84L38

XRT84L38 Datasheet(PDF) 73 Page - Exar Corporation