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2-657
RF5300
Rev A8 051107
Pin
Function
Description
Interface Schematic
1GND
Ground.
2RF IN
RF input. Input is matched to 50
Ω and DC block is provided internally.
3RFIN
Same as pin 2.
See pin 2.
4GND
Ground.
5
VREG1&2
First and second stage input bias. This pin requires a regulated supply
to maintain nominal bias current.
6VREG3/
GND
Ground for third stage bias circuit. Attach to RF ground approximately
100mils to ground from package.
See pin 5.
7VREG3
Third stage input bias. This pin requires a regulated supply to maintain
a nominal bias current.
8VCC3
Third stage supply bias. This pin is sensitive to bypass capacitors
which should be placed approximately 100mils from package and reso-
nate 5GHz to ground.
9GND
Ground.
10
RF OUT
RF output. Output is matched to 50
Ω and DC block is provided.
11
RF OUT
Same as pin 10.
See pin 10.
12
GND
Ground.
13
PWR DET
Provides an output voltage proportional to the RF level.
14
GND
Ground.
15
VCC2
Supply voltage for the second stage. Bypass capacitor is needed to
provide isolation from VCC1 and VCC3.
16
VCC1
Supply voltage for the first stage.
Pkg
Base
GND
Ground connection. The backside of the package should be connected
to the ground plane through a short path (i.e., vias under the device will
be required).
INPUT
MATCH
VCC1
INTERSTAGE
MATCH
BIAS
VREG1
VREG2
BIAS
GND1
BIAS
GND2
RF OUT
OUTPUT
MATCH
VCC2
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