Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

SN74LVC166A Datasheet(PDF) 14 Page - Texas Instruments

Part # SN74LVC166A
Description  SN74LVC166A 8-Bit Parallel-Load Shift Registers with Clear
PDF  23 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74LVC166A Datasheet(HTML) 14 Page - Texas Instruments

Back Button SN74LVC166A Datasheet HTML 10Page - Texas Instruments SN74LVC166A Datasheet HTML 11Page - Texas Instruments SN74LVC166A Datasheet HTML 12Page - Texas Instruments SN74LVC166A Datasheet HTML 13Page - Texas Instruments SN74LVC166A Datasheet HTML 14Page - Texas Instruments SN74LVC166A Datasheet HTML 15Page - Texas Instruments SN74LVC166A Datasheet HTML 16Page - Texas Instruments SN74LVC166A Datasheet HTML 17Page - Texas Instruments SN74LVC166A Datasheet HTML 18Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 14 / 23 page
background image
7 Detailed Description
7.1 Overview
The SN74LVC166A is a parallel-load 8-bit shift register with asynchronous clear ( CLR). This parallel-in or
serial-in, serial-out shift register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input.
The parallel-in or serial-in modes are established by the mode select (SH/LD) input. When high, SH/LD enables
the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When
low, the parallel (A through H) data inputs are enabled, and synchronous loading occurs on the next clock pulse.
During parallel loading, serial data flow is inhibited. Clocking is accomplished on the rising edge of CLK or CLK
INH, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH
high inhibits clocking; holding either low enables the other clock input. CLK INH should be changed to the high
level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
7.2 Functional Block Diagram
D
Q
R
D
Q
R
SER
SH/LD
CLK INH
CLK
CLR
A
B
C
D
E
F
G
H
5 Additional
Shift Register
Stages
D
Q
R
QH
Figure 7-1. Logic Diagram (Positive Logic) for SN74LVC166A
7.3 Feature Description
7.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important to limit the output
power of the device to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs must be left disconnected.
SN74LVC166A
SCLSA15 – MAY 2024
www.ti.com
14
Submit Document Feedback
Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: SN74LVC166A



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com