Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

SAA7221HS/C1 Datasheet(PDF) 3 Page - NXP Semiconductors

Part # SAA7221HS/C1
Description  Integrated MPEG AVGD decoders
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SAA7221HS/C1 Datasheet(HTML) 3 Page - NXP Semiconductors

  SAA7221HS/C1 Datasheet HTML 1Page - NXP Semiconductors SAA7221HS/C1 Datasheet HTML 2Page - NXP Semiconductors SAA7221HS/C1 Datasheet HTML 3Page - NXP Semiconductors SAA7221HS/C1 Datasheet HTML 4Page - NXP Semiconductors SAA7221HS/C1 Datasheet HTML 5Page - NXP Semiconductors SAA7221HS/C1 Datasheet HTML 6Page - NXP Semiconductors SAA7221HS/C1 Datasheet HTML 7Page - NXP Semiconductors SAA7221HS/C1 Datasheet HTML 8Page - NXP Semiconductors SAA7221HS/C1 Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 28 page
background image
2000 Jan 31
3
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
• Vertical scaling with fixed factors 0.5, 0.75, 1 or 2;
factor 0.5 realizes picture shrink. Factor 2 can be used
for up-conversion of pictures with 288 (240) lines or
less; factor 0.75 is used for letterbox presentation.
• Horizontal and vertical scaling can be combined to scale
pictures to 1
⁄4 of their original size, thus freeing up
screen space for graphic applications like electronic
program guides
• Non full screen MPEG pictures can be displayed in a
box of which position and background colour are
adjustable by the external microcontroller; structured
background is available as part of the graphic features
• Nominal video input buffer size for MP at ML 2.7-Mbit
• Video output may be slaved to internally (master)
generated or externally (slave) supplied
HV synchronization signals or CCIR-656 contained
synchronization signals. The position of active video is
programmable. Display phase is not affected by MPEG
timebase changes.
• Decoding and presentation can be independently
handled under CPU control
• Various trick modes under control of external
microcontroller:
– Freeze field/frame on I- or P-frames; restart on
I-picture
– Freeze field on B-frames; restart at any moment
– Scanning and decoding of I- or I- and P-frames in a
IBP sequence
– Single step mode
– Repeat/skip field for time base correction
– Repeat/skip frame for display parity integrity.
• Synchronization modes: DTS controlled, DTS free
running, software controlled, buffer controlled
• DTS register can be set via external controller;
programmable processing delay compensation.
MPEG-2 audio features
• Supported audio sampling frequencies:
48, 44.1, 32, 24, 22.05 and 16 kHz
• Independent channel volume control and programmable
inter-channel crosstalk through a baseband audio
processing unit
• MPEG audio decoder
– Decoding of 2 channels, layer I and II MPEG-1 audio
and low sampling frequency extension of MPEG-2
– Supports for mono, stereo, intensity stereo and dual
channel mode
– CRC error detection with automatic mute
– Constant and variable bit rates up to 448 kbit/s
– Selectable output channel in dual channel mode
– Storage of last 54 bytes in ancillary data field
– Dynamic range control at output.
• Muting possibility via external controller; automatic
muting in case of errors
• Generation of ‘beeps’ with programmable tone height,
duration and amplitude
• Linear PCM decoding
– Support for up to 8 channels linear PCM elementary
audio streams
– Supports for 8, 16, 20 and 24 bit/sample
– Supports for bit rates up to 6.144 Mbit/s
– 96 kHz LPCM samples will be mapped to a 48 kHz
multi-channel format
– Volume control for linear PCM samples in three
steps:
−6, −12 and −18 dB.
• Burst-formatting for interconnection with an external
multi-channel decoder
– AC-3 elementary streams (IEC1937)
– MPEG-2 multi-channel streams in ES or PES format
– Output via the digital audio output or the IEC 958
output.
• Output stage
– Global control for volume and balance
– Serial multi-channel digital audio output with 16, 18,
20 or 22 bits per sample, compatible either to I2Sor
Japanese formats; output can be set to high
impedance mode via the external controller
– IEC958 (Serial SPDIF) audio output; output can be
set to high impedance mode
– Clock output 256 or 384
× fs for external
DA converter or clock input; output can be set to high
impedance mode.
• Audio FIFO in external SDRAM; programmable buffer
size, at least 64 kbit is available
• Synchronization modes: PTS controlled, PTS free
running, software controlled, buffer controlled
• PTS register can be set via external controller;
programmable processing delay compensation.
Background colour
• 24 bit YCbCr colour.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com