SCN68661 datasheet(13/19 Pages) PHILIPS

13 / 19 page

Philips Semiconductors

Product specification

SCN2661/SCN68661

Enhanced programmable communications

interface (EPCI)

1994 Apr 27

Table 9.

68661 EPCI vs 2651 PCI

FEATURE

EPCI

PCI

1. MR2 BIT 6, 7

Control pins 9, 25

Not used

2. DLE detect – SR3

SR3 = 0 for DLE–DLE, DLE – SYN1

SR3 = 1 for DLE–DLE, DLE – SYN1

3. Reset of SR3, DLE detect

Second character after DLE, or receiver

disable, or CR4 = 1

Receiver disable, or CR4 = 1

4. Send DLE – CR3

One time command

Reset via CR3 on next TxRDY

5. DLE stuffing in transparent mode

Automatic DLE stuffing when DLE is loaded

except if CR3 = 1

None

6. SYN1

stripping

double

sync

non-transparent mode

All SYN1

First SYN1 of pair

7. Baud rate versions

Three

One

8. Terminate ASYNC transmission (drop

RTS)

Reset CR5 in response to TxEMT changing

from 1 to 0

Reset CR0 when TxEMT goes from 1 to 0.

Then reset CR5 when TxEMT goes from

1 to 0

9. Break detect

Pin 25*

FE and null character

10. Stop bit searched

One

Two

11. External jam sync

Pin 9**

12. Data bus timing

Improved over 2651

—

13. Data bus drivers

Sink 2.2mA

Source 400

µA

Sink 1.6mA

Source 100

µA

NOTES:

Internal BRG used for RxC.

** Internal BRG used for TxC.

AC LOAD CONDITIONS

CL = 150pF

NOTES:

Open-drain outputs.

CL = Load capacitance includes JIG and probe capacitance.

2.2V

OUTPUT

750

Ω

CL = 50pF

+5V

OUTPUT

Ω

SD00080

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