Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

SRC4382IPFBT Datasheet(PDF) 39 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation.
Part # SRC4382IPFBT
Description  Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver and Transmitter
PDF  81 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  BURR-BROWN [Burr-Brown (TI)]
Direct Link  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

SRC4382IPFBT Datasheet(HTML) 39 Page - Burr-Brown (TI)

Back Button SRC4382IPFBT Datasheet HTML 35Page - Burr-Brown (TI) SRC4382IPFBT Datasheet HTML 36Page - Burr-Brown (TI) SRC4382IPFBT Datasheet HTML 37Page - Burr-Brown (TI) SRC4382IPFBT Datasheet HTML 38Page - Burr-Brown (TI) SRC4382IPFBT Datasheet HTML 39Page - Burr-Brown (TI) SRC4382IPFBT Datasheet HTML 40Page - Burr-Brown (TI) SRC4382IPFBT Datasheet HTML 41Page - Burr-Brown (TI) SRC4382IPFBT Datasheet HTML 42Page - Burr-Brown (TI) SRC4382IPFBT Datasheet HTML 43Page - Burr-Brown (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 39 / 81 page
background image
www.ti.com
A6
A5
A4
A3
A2
A1
A0
1
1
1
0
0
A1
A0
R/W
Se
y
t b Pin 9
1
Se
y
t b Pin 1
2
MSB
LSB
Fir t
s Byte After
o
it
the
R
STA T/RESTART C
o
nd i n
Slave Address
A6
A5
A4
A3
A2
A1
A0
INC
MSB
LSB
(a) SRC438
lave
2 S
Address
(b) Regist r Addre
e
ss Byte
Auto-In
e
crem nt
0 = Disabled
1 = Enabled
S
A
A
A P
S
A
A
A
A
A P
Byte 1
Slave Address
with R/W = 0
Byte 2
Register Address Byte
with INC = 0
Byte 3
Reg st
i er
Da a
t
Byte 1
Slave Address
with R/W = 0
Byte 2
Register Address Byte
with INC = 1
Byte 3
Register Data
Byte 4
Register Data
Fo Add
r
ress + 1
Byte N
Register Data
For Address + N
(a) Writing a Single Register
(b)
r
W iting
ult
isters Using uto-Incr m nt Operation
M
ip
A
e
le Se uential R g
q
e
e
S = STAR
o
T
n i
Co d ti n
A = Acknowl d e
e g
P = STOP Condi i n
t o
Transfer from
ste
Ma
r to Slave
Transfer from Slave to Master
Legend
SRC4382
SBFS030B – JANUARY 2006 – REVISED APRIL 2006
Figure 78 illustrates the protocol for Standard and Fast mode Read operations. The current address read
operation of Figure 78(a) assumes the value of the register address from the previously executed write or read
operation, and is useful for polling a register address for status changes. Figure 78(b) and Figure 78(c) illustrate
read operations for one or more random register addresses, with or without auto-increment mode enabled.
Figure 76. SRC4382 Slave Address and Register Address Byte Definitions
Figure 77. Fast/Standard Mode Write Operations
39
Submit Documentation Feedback



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com