SST85LD0256 datasheet(5/73 Pages) SST

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Advance Information

NANDrive

SST85LD0128 / SST85LD0256 / SST85LD0512

S71319-03-000

2/07

1.0 GENERAL DESCRIPTION

The

SST85LD0128/0256/0512

devices

contain

integrated ATA Controller and NAND Flash die in a LBGA

package. Refer to Figure 2-1 for the NANDrive block

diagram.

1.1 Performance-optimized NANDrive

The heart of the NANDrive is the ATA Flash Disk Controller

which translates standard ATA signals into flash media data

and control signals. The following components contribute to

the NANDrive’s operation.

1.1.1 Microcontroller Unit (MCU)

The MCU translates ATA/IDE commands into data and

control signals required for flash media operation.

1.1.2 Internal Direct Memory Access (DMA)

The NANDrive uses internal DMA allowing instant data

transfer from buffer to flash media. This implementation

eliminates microcontroller overhead associated with the

traditional, firmware-based approach, thereby increasing

the data transfer rate.

1.1.3 Power Management Unit (PMU)

The

power

management

unit

controls

the

power

consumption of the NANDrive. The PMU dramatically

reduces the power consumption of the NANDrive by

putting the part of the circuitry that is not in operation into

sleep mode.

1.1.4 SRAM Buffer

A key contributor to the NANDrive performance is an

SRAM buffer. The buffer optimizes the host’s data transfer

to and from the flash media.

1.1.5 Embedded Flash File System

The embedded flash file system is an integral part of the

NANDrive. It contains MCU firmware that performs the

following tasks:

1. Translates host side signals into flash media

writes and reads.

2. Provides dynamic flash media wear leveling to

spread the flash writes across all unused memory

address space to increase the longevity of flash

media.

3. Keeps track of data file structures.

4. Manages system security for the selected

protection zones.

1.1.6 Error Correction Code (ECC)

The

NANDrive

utilizes

72-bit

Reed-Solomon

Error

Detection Code (EDC) and Error Correction Code (ECC),

which provides the following error immunity for each 512-

byte block of data:

1. Corrects up to three random 12-bit symbol errors.

2. Corrects single bursts up to 25 bits.

3. Detects single bursts up to 61 bits and double

bursts up to 15 bits.

4. Detects up to six random 12-bit symbol errors.

1.1.7 Serial Communication Interface (SCI)

The Serial Communication Interface (SCI) is designed for

manufacturing error reporting.

1.1.8 Multi-tasking Interface

The multi-tasking interface enables fast, sustained write

performance by allowing concurrent Read, Program, and

Erase operations to multiple flash media devices.

1.2 NAND Flash

The SST85LD0128/0256/0512 devices utilize standard

NAND Flash for data storage.

SST85LD0256 Datasheet(PDF) 5 Page - Silicon Storage Technology, Inc

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